*PIN.17 (DBGRQ) Asynchronous debug request. DBGRQ allows an external signal to force the ARM core into debug mode, should be pull down to GND.
PIN.19 (DBGACK) Debug acknowledge. The ARM core acknowledges debug-mode inresponse to a DBGRQ input.
+
+----------- SAMPLE TIMES -----------
+
+TDI and TMS are sampled on the rising edge of TCK and TDO transitions appear on the falling edge of TCK. Therefore, TDI and TMS must be written after the falling edge of TCK and TDO must be read after the rising edge of TCK.
+
+for this module, we keep tck high for all changes/sampling, and then bounce it.
****************************************************************/
+
/************************** JTAGARM7TDMI Primitives ****************************/
void jtag_goto_shift_ir() {
SETTMS;
PLEDOUT^=PLEDPIN;
}
+
// ! Start JTAG, setup pins, reset TAP and return IDCODE
unsigned long jtagarm7tdmi_start() {
jtagsetup();
SETTST;
SETRST;
- delay(0xF);
+ delay(0x2);
CLRRST;
- delay(20);
+ delay(2);
CLRTST;
msdelay(10);
/*
P5DIR &=~RST;
*/
- delay(0xF);
+ delay(0x2);
jtagarm7tdmi_resettap();
return jtagarm7tdmi_idcode();
}
unsigned long high = 1;
unsigned long mask;
- for (bit=(bitcount-1)/16; bit>0; bit--)
- high <<= 16;
- high <<= ((bitcount-1)%16);
+ for (bit=(bitcount-1)/8; bit>0; bit--)
+ high <<= 8;
+ high <<= ((bitcount-1)%8);
mask = high-1;
}
}
} else {
- for (bit=bitcount; bit>0; bit++) {
+ for (bit = bitcount; bit > 0; bit--) {
/* write MOSI on trailing edge of previous clock */
if (word & high)
{SETMOSI;}
//! Connect Bypass Register to TDO/TDI
unsigned char jtagarm7tdmi_bypass(){ // PROVEN
- jtagarm7tdmi_resettap();
+ //jtagarm7tdmi_resettap();
SHIFT_IR;
return jtagarmtransn(ARM7TDMI_IR_BYPASS, 4, LSB, END, NORETIDLE);
}
//! INTEST verb - do internal test
unsigned char jtagarm7tdmi_intest() {
- jtagarm7tdmi_resettap();
+ //jtagarm7tdmi_resettap();
SHIFT_IR;
return jtagarmtransn(ARM7TDMI_IR_INTEST, 4, LSB, END, NORETIDLE);
}
//! EXTEST verb
unsigned char jtagarm7tdmi_extest() {
- jtagarm7tdmi_resettap();
+ //jtagarm7tdmi_resettap();
SHIFT_IR;
return jtagarmtransn(ARM7TDMI_IR_EXTEST, 4, LSB, END, NORETIDLE);
}
//! RESTART verb
unsigned char jtagarm7tdmi_restart() {
- jtagarm7tdmi_resettap();
+ //jtagarm7tdmi_resettap();
SHIFT_IR;
return jtagarmtransn(ARM7TDMI_IR_RESTART, 4, LSB, END, RETIDLE);
}
-//! push an instruction into the pipeline - Assumes scan-chain 1 is already INTEST
+//! push an instruction into the pipeline
unsigned long jtagarm7tdmi_instr_primitive(unsigned long instr, char breakpt){
unsigned long retval;
+ //jtagarm7tdmi_resettap(); // FIXME: DEBUG: seems necessary for some reason. ugh.
jtagarm7tdmi_scan_intest(1);
SHIFT_DR;
cmddataword[4] = jtagarm7tdmi_instr_primitive(THUMB_INSTR_BX_PC,0);
cmddataword[5] = jtagarm7tdmi_instr_primitive(THUMB_INSTR_NOP,0);
cmddataword[6] = jtagarm7tdmi_instr_primitive(THUMB_INSTR_NOP,0);
- delay(10);
jtagarm7tdmi_resettap(); // seems necessary for some reason. ugh.
}
return(retval);
return retval;
}
+//! Retrieve a 32-bit Register value
+unsigned long test_get_register(unsigned char reg) {
+ unsigned long retval = 0, instr;
+ // push nop into pipeline - clean out the pipeline...
+ cmddatalong[2] = jtagarm7tdmi_nop( 0);
+
+ instr = ARM_READ_REG | (reg<<12); // push STR Rx, [R14] into pipeline
+ cmddatalong[1] = jtagarm7tdmi_instr_primitive(instr, 0); // fetch
+ cmddatalong[2] = jtagarm7tdmi_nop( 0); // decode
+ cmddatalong[3] = jtagarm7tdmi_nop( 0); // execute
+ cmddatalong[4] = jtagarm7tdmi_nop( 0); // ??? what happens here ???
+ retval = jtagarm7tdmi_nop( 0); // recover 32-bit word
+ cmddatalong[5] = retval;
+ cmddatalong[6] = jtagarm7tdmi_nop( 0);
+ cmddatalong[7] = jtagarm7tdmi_nop( 0);
+ cmddatalong[8] = jtagarm7tdmi_nop( 0);
+ return retval;
+}
+
//! Set a 32-bit Register value
unsigned long jtagarm7tdmi_set_register(unsigned char reg, unsigned long val) {
unsigned long retval = 0, instr;
- cmddatalong[2] = jtagarm7tdmi_nop( 0); // push nop into pipeline - clean out the pipeline...
+ cmddatalong[1] = jtagarm7tdmi_nop( 0); // push nop into pipeline - clean out the pipeline...
instr = ARM_WRITE_REG | (reg<<12); // push LDR Rx, [R14] into pipeline
- cmddatalong[1] = jtagarm7tdmi_instr_primitive(instr, 0);
- cmddatalong[2] = jtagarm7tdmi_nop( 0); // push nop into pipeline - fetched
- cmddatalong[3] = jtagarm7tdmi_nop( 0); // push nop into pipeline - decoded
+ cmddatalong[2] = jtagarm7tdmi_instr_primitive(instr, 0); // push nop into pipeline - fetch
+ cmddatalong[3] = jtagarm7tdmi_nop( 0); // push nop into pipeline - decode
+ cmddatalong[4] = jtagarm7tdmi_instr_primitive(val-16, 0); // push 32-bit word on data bus
+ //cmddatalong[4] = jtagarm7tdmi_nop( 0); // push nop into pipeline - execute
- cmddatalong[4] = jtagarm7tdmi_instr_primitive(val, 0); // push 32-bit word on data bus - execute state
- cmddatalong[5] = jtagarm7tdmi_nop( 0); // push nop into pipeline - executed
+ cmddatalong[5] = jtagarm7tdmi_instr_primitive(val, 0); // push 32-bit word on data bus
+ cmddatalong[6] = jtagarm7tdmi_instr_primitive(val+16, 0); // push 32-bit word on data bus
+ //cmddatalong[6] = jtagarm7tdmi_nop( 0); // push nop into pipeline - executed
if (reg == ARM_REG_PC){
- cmddatalong[6] = jtagarm7tdmi_nop( 0);
cmddatalong[7] = jtagarm7tdmi_nop( 0);
+ cmddatalong[8] = jtagarm7tdmi_nop( 0);
}
- cmddatalong[8] = jtagarm7tdmi_nop( 0);
+ cmddatalong[9] = jtagarm7tdmi_nop( 0);
+
+ retval = cmddatalong[5];
+ return(retval);
+}
+
+//! Set a 32-bit Register value
+unsigned long test_set_register(unsigned char reg, unsigned long val) {
+ unsigned long retval = 0, instr;
+ cmddatalong[1] = jtagarm7tdmi_nop( 0); // push nop into pipeline - clean out the pipeline...
+
+ instr = ARM_WRITE_REG | (reg<<12); // push LDR Rx, [R14] into pipeline
+ cmddatalong[2] = jtagarm7tdmi_instr_primitive(instr, 0);
+
+ cmddatalong[3] = jtagarm7tdmi_instr_primitive(val+32, 0); // push 32-bit word on data bus - execute state
+ cmddatalong[4] = jtagarm7tdmi_instr_primitive(val+16, 0); // push 32-bit word on data bus - execute state
+ cmddatalong[5] = jtagarm7tdmi_instr_primitive(val, 0); // push 32-bit word on data bus - execute state
+ cmddatalong[6] = jtagarm7tdmi_instr_primitive(val-16, 0); // push 32-bit word on data bus - execute state
+
+ if (reg == ARM_REG_PC){
+ cmddatalong[7] = jtagarm7tdmi_nop( 0);
+ cmddatalong[8] = jtagarm7tdmi_nop( 0);
+ }
+ cmddatalong[9] = jtagarm7tdmi_instr_primitive(val-32, 0); // push 32-bit word on data bus - execute state
retval = cmddatalong[5];
return(retval);
+
//! Get all registers. Return an array
unsigned long* jtagarm7tdmi_get_registers() {
cmddatalong[1] = jtagarm7tdmi_instr_primitive(ARM_INSTR_SKANKREGS,0);
return registers;
}
+//! Get all registers. Return an array
+unsigned long* jtagarm7tdmi_set_registers() {
+ cmddatalong[1] = jtagarm7tdmi_instr_primitive(ARM_INSTR_SKANKREGS,0);
+ cmddatalong[2] = jtagarm7tdmi_nop( 0);
+ cmddatalong[3] = jtagarm7tdmi_nop( 0);
+ cmddatalong[4] = jtagarm7tdmi_instr_primitive(0x40,0);
+ cmddatalong[5] = jtagarm7tdmi_instr_primitive(0x41,0);
+ cmddatalong[6] = jtagarm7tdmi_instr_primitive(0x42,0);
+ cmddatalong[7] = jtagarm7tdmi_instr_primitive(0x43,0);
+ cmddatalong[8] = jtagarm7tdmi_instr_primitive(0x44,0);
+ cmddatalong[9] = jtagarm7tdmi_instr_primitive(0x45,0);
+ cmddatalong[10] = jtagarm7tdmi_instr_primitive(0x46,0);
+ cmddatalong[11] = jtagarm7tdmi_instr_primitive(0x47,0);
+ cmddatalong[12] = jtagarm7tdmi_instr_primitive(0x48,0);
+ cmddatalong[13] = jtagarm7tdmi_instr_primitive(0x49,0);
+ cmddatalong[14] = jtagarm7tdmi_instr_primitive(0x4a,0);
+ cmddatalong[15] = jtagarm7tdmi_instr_primitive(0x4b,0);
+ cmddatalong[16] = jtagarm7tdmi_instr_primitive(0x4c,0);
+ cmddatalong[17] = jtagarm7tdmi_instr_primitive(0x4d,0);
+ cmddatalong[18] = jtagarm7tdmi_instr_primitive(0x4e,0);
+ cmddatalong[19] = jtagarm7tdmi_instr_primitive(0x4f,0);
+ return registers;
+}
+
//! Retrieve the CPSR Register value
unsigned long jtagarm7tdmi_get_regCPSR() {
unsigned long retval = 0;
delay(1);
waitcount --;
}
- if (waitcount == 0xffff){
+ if (waitcount == 0){
return (-1);
} else {
retval = jtagarm7tdmi_get_register(1); // read memory value from R1 register
- jtagarm7tdmi_set_register(1, r1); // restore R0 and R1
- jtagarm7tdmi_set_register(0, r0);
+ jtagarm7tdmi_set_register(1, r1); // restore R0 and R1
+ jtagarm7tdmi_set_register(0, r0);
}
return retval;
}
// poll until debug status says the cpu is in debug mode
while (!(jtagarm7tdmi_get_dbgstate() & 0x1) && waitcount-- > 0){
- delay(5);
+ delay(1);
}
eice_write(EICE_WP1CTRL, 0x0); // write 0 in watchpoint 0 control value - disables watchpoint 0
while (jtagarm7tdmi_get_dbgstate() & JTAG_ARM7TDMI_DBG_TBIT && waitcount-- > 0) {
jtagarm7tdmi_setMode_ARM();
}
+ jtagarm7tdmi_resettap();
return waitcount;
}
instr = ARM_INSTR_B_PC + 0x1000001 - (count_dbgspd_instr_since_debug) - (count_sysspd_instr_since_debug*3); //FIXME: make this right - can't we just do an a7solute b/bx?
jtagarm7tdmi_instr_primitive(instr,0);
} else {
- instr = ARM_INSTR_B_PC + 0x1000000 - (count_dbgspd_instr_since_debug) - (count_sysspd_instr_since_debug*3); //FIXME: make this right - can't we just do an absolute b/bx?
+ instr = ARM_INSTR_B_PC + 0x1000000 - (count_dbgspd_instr_since_debug*4) - (count_sysspd_instr_since_debug*12);
jtagarm7tdmi_instr_primitive(instr,0);
}
// wait until restart-bit set in debug state register
while ((jtagarm7tdmi_get_dbgstate() & JTAG_ARM7TDMI_DBG_DBGACK) && waitcount > 0){
- //delay(1);
+ msdelay(1);
waitcount --;
}
last_halt_debug_state = -1;
void jtagarm7tdmihandle(unsigned char app, unsigned char verb, unsigned long len){
register char blocks;
- unsigned int i,val;
+ unsigned int i,val,mlop;
unsigned long at;
jtagarm7tdmi_resettap();
cmddatalong[2] = jtagarm7tdmi_haltcpu();
//jtagarm7tdmi_resettap();
cmddatalong[1] = jtagarm7tdmi_get_dbgstate();
-
+
+ // DEBUG: FIXME: NOT PART OF OPERATIONAL CODE
+ //for (mlop=2;mlop<4;mlop++){
+ // jtagarm7tdmi_set_register(mlop, 0x43424140);
+ //}
+ /////////////////////////////////////////////
txdata(app,verb,0xc);
break;
case JTAGARM7TDMI_READMEM:
case JTAGARM7TDMI_GET_REGISTER:
jtagarm7tdmi_resettap();
cmddatalong[0] = jtagarm7tdmi_get_register(cmddata[0]);
+ //cmddatalong[0] = test_get_register(cmddata[0]);
txdata(app,verb,96);
break;
- case JTAGARM7TDMI_SET_REGISTER:
+ case JTAGARM7TDMI_SET_REGISTER: // FIXME: NOT AT ALL CORRECT, THIS IS TESTING CODE ONLY
jtagarm7tdmi_resettap();
cmddatalong[0] = cmddatalong[1];
jtagarm7tdmi_set_register(cmddata[0], cmddatalong[1]);
+ //test_set_register(cmddata[0], cmddatalong[1]);
txdata(app,verb,96);
break;
case JTAGARM7TDMI_GET_REGISTERS:
jtagarm7tdmi_resettap();
jtagarm7tdmi_get_registers();
- txdata(app,verb,80);
+ txdata(app,verb,200);
+ break;
+ case JTAGARM7TDMI_SET_REGISTERS:
+ jtagarm7tdmi_resettap();
+ jtagarm7tdmi_set_registers();
+ txdata(app,verb,200);
break;
- //case JTAGARM7TDMI_SET_REGISTERS:
case JTAGARM7TDMI_DEBUG_INSTR:
jtagarm7tdmi_resettap();
cmddataword[0] = jtagarm7tdmi_exec(cmddataword[0], cmddataword[1], cmddata[9]);
txdata(app,verb,80);
break;
- case JTAGARM7TDMI_STEP_INSTR:
+ //case JTAGARM7TDMI_STEP_INSTR:
/* case JTAGARM7TDMI_READ_CODE_MEMORY:
case JTAGARM7TDMI_WRITE_FLASH_PAGE:
case JTAGARM7TDMI_READ_FLASH_PAGE:
cmddatalong[9] = jtagarmtransn(0x44444444, 1, MSB, NOEND, NORETIDLE);
cmddatalong[10] = jtagarmtransn(cmddatalong[8], 32, MSB, NOEND, NORETIDLE);
cmddatalong[11] = jtagarmtransn(cmddatalong[9], 1, MSB, END, RETIDLE);
+ jtagarm7tdmi_resettap();
txdata(app,verb,48);
break;
jtaghandle(app,verb,len);
}
}
+
+
+
+
+/*****************************
+Captured from FlySwatter against AT91SAM7S, to be used by me for testing. ignore
+
+> arm reg
+System and User mode registers
+ r0: 300000df r1: 00000000 r2: 58000000 r3: 00200a75
+ r4: fffb0000 r5: 00000002 r6: 00000000 r7: 00200f6c
+ r8: 00000000 r9: 00000000 r10: ffffffff r11: 00000000
+ r12: 00000009 sp_usr: 00000000 lr_usr: 00000000 pc: 000000fc
+ cpsr: 00000093
+
+FIQ mode shadow registers
+ r8_fiq: 00000000 r9_fiq: fffcc000 r10_fiq: fffff400 r11_fiq: fffff000
+ r12_fiq: 00200f44 sp_fiq: 00000000 lr_fiq: 00000000 spsr_fiq: f00000fb
+
+Supervisor mode shadow registers
+ sp_svc: 00201f78 lr_svc: 00200a75 spsr_svc: 400000b3
+
+Abort mode shadow registers
+ sp_abt: 00000000 lr_abt: 00000000 spsr_abt: e00000ff
+
+IRQ mode shadow registers
+ sp_irq: 00000000 lr_irq: 00000000 spsr_irq: f000003b
+
+Undefined instruction mode shadow registers
+ sp_und: 00000000 lr_und: 00000000 spsr_und: 300000df
+>
+> step;arm reg
+target state: halted
+target halted in ARM state due to single-step, current mode: Supervisor
+cpsr: 0x00000093 pc: 0x00000100
+System and User mode registers
+ r0: 300000df r1: 00000000 r2: 00200000 r3: 00200a75
+ r4: fffb0000 r5: 00000002 r6: 00000000 r7: 00200f6c
+ r8: 00000000 r9: 00000000 r10: ffffffff r11: 00000000
+ r12: 00000009 sp_usr: 00000000 lr_usr: 00000000 pc: 00000100
+ cpsr: 00000093
+
+FIQ mode shadow registers
+ r8_fiq: 00000000 r9_fiq: fffcc000 r10_fiq: fffff400 r11_fiq: fffff000
+ r12_fiq: 00200f44 sp_fiq: 00000000 lr_fiq: 00000000 spsr_fiq: f00000fb
+
+Supervisor mode shadow registers
+ sp_svc: 00201f78 lr_svc: 00200a75 spsr_svc: 400000b3
+
+Abort mode shadow registers
+ sp_abt: 00000000 lr_abt: 00000000 spsr_abt: e00000ff
+
+IRQ mode shadow registers
+ sp_irq: 00000000 lr_irq: 00000000 spsr_irq: f000003b
+
+Undefined instruction mode shadow registers
+ sp_und: 00000000 lr_und: 00000000 spsr_und: 300000df
+>
+ step;arm reg
+target state: halted
+target halted in ARM state due to single-step, current mode: Abort
+cpsr: 0x00000097 pc: 0x00000010
+System and User mode registers
+ r0: 300000e3 r1: 00000000 r2: 00200000 r3: 00200a75
+ r4: fffb0000 r5: 00000002 r6: 00000000 r7: 00200f6c
+ r8: 00000000 r9: 00000000 r10: ffffffff r11: 00000000
+ r12: 00000009 sp_usr: 00000000 lr_usr: 00000000 pc: 00000010
+ cpsr: 00000097
+
+FIQ mode shadow registers
+ r8_fiq: 00000000 r9_fiq: fffcc000 r10_fiq: fffff400 r11_fiq: fffff000
+ r12_fiq: 00200f44 sp_fiq: 00000000 lr_fiq: 00000000 spsr_fiq: f00000fb
+
+Supervisor mode shadow registers
+ sp_svc: 00201f78 lr_svc: 00200a75 spsr_svc: 400000b3
+
+Abort mode shadow registers
+ sp_abt: 00000000 lr_abt: 00000108 spsr_abt: 00000093
+
+IRQ mode shadow registers
+ sp_irq: 00000000 lr_irq: 00000000 spsr_irq: f000003b
+
+Undefined instruction mode shadow registers
+ sp_und: 00000000 lr_und: 00000000 spsr_und: 300000df
+> step;arm reg
+target state: halted
+target halted in ARM state due to single-step, current mode: Abort
+cpsr: 0x00000097 pc: 0x00000010
+System and User mode registers
+ r0: 300000e3 r1: 00000000 r2: 00200000 r3: 00200a75
+ r4: fffb0000 r5: 00000002 r6: 00000000 r7: 00200f6c
+ r8: 00000000 r9: 00000000 r10: ffffffff r11: 00000000
+ r12: 00000009 sp_usr: 00000000 lr_usr: 00000000 pc: 00000010
+ cpsr: 00000097
+
+FIQ mode shadow registers
+ r8_fiq: 00000000 r9_fiq: fffcc000 r10_fiq: fffff400 r11_fiq: fffff000
+ r12_fiq: 00200f44 sp_fiq: 00000000 lr_fiq: 00000000 spsr_fiq: f00000fb
+
+Supervisor mode shadow registers
+ sp_svc: 00201f78 lr_svc: 00200a75 spsr_svc: 400000b3
+
+Abort mode shadow registers
+ sp_abt: 00000000 lr_abt: 00000108 spsr_abt: 00000093
+
+IRQ mode shadow registers
+ sp_irq: 00000000 lr_irq: 00000000 spsr_irq: f000003b
+
+Undefined instruction mode shadow registers
+ sp_und: 00000000 lr_und: 00000000 spsr_und: 300000df
+> step;arm reg
+target state: halted
+target halted in ARM state due to single-step, current mode: Abort
+cpsr: 0x00000097 pc: 0x00000010
+System and User mode registers
+ r0: 300000e3 r1: 00000000 r2: 00200000 r3: 00200a75
+ r4: fffb0000 r5: 00000002 r6: 00000000 r7: 00200f6c
+ r8: 00000000 r9: 00000000 r10: ffffffff r11: 00000000
+ r12: 00000009 sp_usr: 00000000 lr_usr: 00000000 pc: 00000010
+ cpsr: 00000097
+
+FIQ mode shadow registers
+ r8_fiq: 00000000 r9_fiq: fffcc000 r10_fiq: fffff400 r11_fiq: fffff000
+ r12_fiq: 00200f44 sp_fiq: 00000000 lr_fiq: 00000000 spsr_fiq: f00000fb
+
+Supervisor mode shadow registers
+ sp_svc: 00201f78 lr_svc: 00200a75 spsr_svc: 400000b3
+
+Abort mode shadow registers
+ sp_abt: 00000000 lr_abt: 00000108 spsr_abt: 00000093
+
+IRQ mode shadow registers
+ sp_irq: 00000000 lr_irq: 00000000 spsr_irq: f000003b
+
+Undefined instruction mode shadow registers
+ sp_und: 00000000 lr_und: 00000000 spsr_und: 300000df
+> step;arm reg
+target state: halted
+target halted in ARM state due to single-step, current mode: Abort
+cpsr: 0x00000097 pc: 0x00000010
+System and User mode registers
+ r0: 300000e3 r1: 00000000 r2: 00200000 r3: 00200a75
+ r4: fffb0000 r5: 00000002 r6: 00000000 r7: 00200f6c
+ r8: 00000000 r9: 00000000 r10: ffffffff r11: 00000000
+ r12: 00000009 sp_usr: 00000000 lr_usr: 00000000 pc: 00000010
+ cpsr: 00000097
+
+FIQ mode shadow registers
+ r8_fiq: 00000000 r9_fiq: fffcc000 r10_fiq: fffff400 r11_fiq: fffff000
+ r12_fiq: 00200f44 sp_fiq: 00000000 lr_fiq: 00000000 spsr_fiq: f00000fb
+
+Supervisor mode shadow registers
+ sp_svc: 00201f78 lr_svc: 00200a75 spsr_svc: 400000b3
+
+Abort mode shadow registers
+ sp_abt: 00000000 lr_abt: 00000108 spsr_abt: 00000093
+
+IRQ mode shadow registers
+ sp_irq: 00000000 lr_irq: 00000000 spsr_irq: f000003b
+
+Undefined instruction mode shadow registers
+ sp_und: 00000000 lr_und: 00000000 spsr_und: 300000df
+> step;arm reg
+target state: halted
+target halted in ARM state due to single-step, current mode: Abort
+cpsr: 0x00000097 pc: 0x00000010
+System and User mode registers
+ r0: 300000e3 r1: 00000000 r2: 00200000 r3: 00200a75
+ r4: fffb0000 r5: 00000002 r6: 00000000 r7: 00200f6c
+ r8: 00000000 r9: 00000000 r10: ffffffff r11: 00000000
+ r12: 00000009 sp_usr: 00000000 lr_usr: 00000000 pc: 00000010
+ cpsr: 00000097
+
+FIQ mode shadow registers
+ r8_fiq: 00000000 r9_fiq: fffcc000 r10_fiq: fffff400 r11_fiq: fffff000
+ r12_fiq: 00200f44 sp_fiq: 00000000 lr_fiq: 00000000 spsr_fiq: f00000fb
+
+Supervisor mode shadow registers
+ sp_svc: 00201f78 lr_svc: 00200a75 spsr_svc: 400000b3
+
+Abort mode shadow registers
+ sp_abt: 00000000 lr_abt: 00000108 spsr_abt: 00000093
+
+IRQ mode shadow registers
+ sp_irq: 00000000 lr_irq: 00000000 spsr_irq: f000003b
+
+Undefined instruction mode shadow registers
+ sp_und: 00000000 lr_und: 00000000 spsr_und: 300000df
+> step;arm reg
+target state: halted
+target halted in ARM state due to single-step, current mode: Abort
+cpsr: 0x00000097 pc: 0x00000010
+System and User mode registers
+ r0: 300000e3 r1: 00000000 r2: 00200000 r3: 00200a75
+ r4: fffb0000 r5: 00000002 r6: 00000000 r7: 00200f6c
+ r8: 00000000 r9: 00000000 r10: ffffffff r11: 00000000
+ r12: 00000009 sp_usr: 00000000 lr_usr: 00000000 pc: 00000010
+ cpsr: 00000097
+
+FIQ mode shadow registers
+ r8_fiq: 00000000 r9_fiq: fffcc000 r10_fiq: fffff400 r11_fiq: fffff000
+ r12_fiq: 00200f44 sp_fiq: 00000000 lr_fiq: 00000000 spsr_fiq: f00000fb
+
+Supervisor mode shadow registers
+ sp_svc: 00201f78 lr_svc: 00200a75 spsr_svc: 400000b3
+
+Abort mode shadow registers
+ sp_abt: 00000000 lr_abt: 00000108 spsr_abt: 00000093
+
+IRQ mode shadow registers
+ sp_irq: 00000000 lr_irq: 00000000 spsr_irq: f000003b
+
+Undefined instruction mode shadow registers
+ sp_und: 00000000 lr_und: 00000000 spsr_und: 300000df
+> step;arm reg
+target state: halted
+target halted in ARM state due to single-step, current mode: Abort
+cpsr: 0x00000097 pc: 0x00000010
+System and User mode registers
+ r0: 300000e3 r1: 00000000 r2: 00200000 r3: 00200a75
+ r4: fffb0000 r5: 00000002 r6: 00000000 r7: 00200f6c
+ r8: 00000000 r9: 00000000 r10: ffffffff r11: 00000000
+ r12: 00000009 sp_usr: 00000000 lr_usr: 00000000 pc: 00000010
+ cpsr: 00000097
+
+FIQ mode shadow registers
+ r8_fiq: 00000000 r9_fiq: fffcc000 r10_fiq: fffff400 r11_fiq: fffff000
+ r12_fiq: 00200f44 sp_fiq: 00000000 lr_fiq: 00000000 spsr_fiq: f00000fb
+
+Supervisor mode shadow registers
+ sp_svc: 00201f78 lr_svc: 00200a75 spsr_svc: 400000b3
+
+Abort mode shadow registers
+ sp_abt: 00000000 lr_abt: 00000108 spsr_abt: 00000093
+
+IRQ mode shadow registers
+ sp_irq: 00000000 lr_irq: 00000000 spsr_irq: f000003b
+
+Undefined instruction mode shadow registers
+ sp_und: 00000000 lr_und: 00000000 spsr_und: 300000df
+> step;arm reg
+target state: halted
+target halted in ARM state due to single-step, current mode: Abort
+cpsr: 0x00000097 pc: 0x00000010
+System and User mode registers
+ r0: 300000e3 r1: 00000000 r2: 00200000 r3: 00200a75
+ r4: fffb0000 r5: 00000002 r6: 00000000 r7: 00200f6c
+ r8: 00000000 r9: 00000000 r10: ffffffff r11: 00000000
+ r12: 00000009 sp_usr: 00000000 lr_usr: 00000000 pc: 00000010
+ cpsr: 00000097
+
+FIQ mode shadow registers
+ r8_fiq: 00000000 r9_fiq: fffcc000 r10_fiq: fffff400 r11_fiq: fffff000
+ r12_fiq: 00200f44 sp_fiq: 00000000 lr_fiq: 00000000 spsr_fiq: f00000fb
+
+Supervisor mode shadow registers
+ sp_svc: 00201f78 lr_svc: 00200a75 spsr_svc: 400000b3
+
+Abort mode shadow registers
+ sp_abt: 00000000 lr_abt: 00000108 spsr_abt: 00000093
+
+IRQ mode shadow registers
+ sp_irq: 00000000 lr_irq: 00000000 spsr_irq: f000003b
+
+Undefined instruction mode shadow registers
+ sp_und: 00000000 lr_und: 00000000 spsr_und: 300000df
+> step;arm reg
+target state: halted
+target halted in ARM state due to single-step, current mode: Abort
+cpsr: 0x00000097 pc: 0x00000010
+System and User mode registers
+ r0: 300000e3 r1: 00000000 r2: 00200000 r3: 00200a75
+ r4: fffb0000 r5: 00000002 r6: 00000000 r7: 00200f6c
+ r8: 00000000 r9: 00000000 r10: ffffffff r11: 00000000
+ r12: 00000009 sp_usr: 00000000 lr_usr: 00000000 pc: 00000010
+ cpsr: 00000097
+
+FIQ mode shadow registers
+ r8_fiq: 00000000 r9_fiq: fffcc000 r10_fiq: fffff400 r11_fiq: fffff000
+ r12_fiq: 00200f44 sp_fiq: 00000000 lr_fiq: 00000000 spsr_fiq: f00000fb
+
+Supervisor mode shadow registers
+ sp_svc: 00201f78 lr_svc: 00200a75 spsr_svc: 400000b3
+
+Abort mode shadow registers
+ sp_abt: 00000000 lr_abt: 00000108 spsr_abt: 00000093
+
+IRQ mode shadow registers
+ sp_irq: 00000000 lr_irq: 00000000 spsr_irq: f000003b
+
+Undefined instruction mode shadow registers
+ sp_und: 00000000 lr_und: 00000000 spsr_und: 300000df
+>
+