/*! \file ccspi.c
\author Travis Goodspeed
\brief Chipcon SPI Register Interface
-
+
Unfortunately, there is very little similarity between the CC2420
and the CC2500, to name just two of the myriad of Chipcon SPI
radios. Auto-detection will be a bit difficult, but more to the
#include "platform.h"
#include "command.h"
#include <stdlib.h> //added for itoa
-#include <signal.h>
-#include <io.h>
-#include <iomacros.h>
#include "ccspi.h"
#include "spi.h"
SPIDIR|=MOSI+SCK;
DIRSS;
DIRCE;
-
+
P4OUT|=BIT5; //activate CC2420 voltage regulator
msdelay(100);
-
+
//Reset the CC2420.
P4OUT&=~BIT6;
P4OUT|=BIT6;
-
+
//Begin a new transaction.
CLRSS;
SETSS;
register unsigned int bit;
//This function came from the CCSPI Wikipedia article.
//Minor alterations.
-
+
for (bit = 0; bit < 8; bit++) {
/* write MOSI on trailing edge of previous clock */
if (byte & 0x80)
else
CLRMOSI;
byte <<= 1;
-
+
SETCLK;
-
+
/* read MISO on trailing edge */
byte |= READMISO;
CLRCLK;
}
-
+
return byte;
}
//! Writes a register
u8 ccspi_regwrite(u8 reg, const u8 *buf, int len){
CLRSS;
-
+
reg=ccspitrans8(reg);
while(len--)
ccspitrans8(*buf++);
-
+
SETSS;
return reg;//status
}
//! Reads a register
u8 ccspi_regread(u8 reg, u8 *buf, int len){
CLRSS;
-
+
reg=ccspitrans8(reg);
while(len--)
*buf++=ccspitrans8(0);
-
+
SETSS;
return reg;//status
}
uint8_t const verb,
uint32_t const len){
unsigned long i;
-
+ u8 j;
+
//debugstr("Chipcon SPI handler.");
-
+
switch(verb){
case PEEK:
cmddata[0]|=0x40; //Set the read bit.
case WRITE:
case POKE:
CLRSS; //Drop !SS to begin transaction.
+ j=cmddata[0];//Backup address.
for(i=0;i<len;i++)
cmddata[i]=ccspitrans8(cmddata[i]);
SETSS; //Raise !SS to end transaction.
+ cmddata[0]=j&~0x40;//Restore address.
txdata(app,verb,len);
break;
case SETUP:
#ifdef FIFOP
//Has there been an overflow?
if((!FIFO)&&FIFOP){
- debugstr("Clearing overflow");
+ //debugstr("Clearing overflow");
CLRSS;
ccspitrans8(0x08); //SFLUSHRX
SETSS;
}
-
+
//Is there a packet?
if(FIFOP&&FIFO){
//Wait for completion.
for(i=0;i<cmddata[0]+2;i++)
cmddata[i]=ccspitrans8(0xde);
SETSS;
-
+
//Flush buffer.
CLRSS;
ccspitrans8(0x08); //SFLUSHRX
SETSS;
+
+
//Only should transmit length of one more than the reported
// length of the frame, which holds the length byte:
txdata(app,verb,cmddata[0]+1);
CLRSS;
ccspitrans8(CCSPI_SFLUSHRX);
SETSS;
-
+
txdata(app,verb,0);
break;
CLRSS;
ccspitrans8(CCSPI_SFLUSHTX);
SETSS;
-
+
txdata(app,verb,0);
break;
case CCSPI_TX:
#ifdef FIFOP
-
+
//Wait for last packet to TX.
//while(ccspi_status()&BIT3);
+ //Flush TX buffer.
+ CLRSS;
+ ccspitrans8(0x09); //SFLUSHTX
+ SETSS;
+
+
//Load the packet.
CLRSS;
ccspitrans8(CCSPI_TXFIFO);
for(i=0;i<cmddata[0];i++)
ccspitrans8(cmddata[i]);
SETSS;
-
+
//Transmit the packet.
CLRSS;
ccspitrans8(0x04); //STXON
SETSS;
-
+
//Wait for the pulse on SFD, after which the packet has been sent.
while(!SFD);
while(SFD);
- //Flush TX buffer.
- CLRSS;
- ccspitrans8(0x09); //SFLUSHTX
- SETSS;
-
txdata(app,verb,0);
#else
debugstr("Can't TX a packet with SFD and FIFOP definitions.");