DIRSS;
DIRCE;
- P4OUT|=BIT5; //activate CC2420 voltage regulator
+ //P4OUT|=BIT5; //activate CC2420 voltage regulator
msdelay(100);
//Reset the CC2420.
- P4OUT&=~BIT6;
- P4OUT|=BIT6;
+ /*P4OUT&=~BIT6; FIXME Does the new code work on Z1 and Telosb?
+ P4OUT|=BIT6;*/
+ CLRCE;
+ SETCE;
//Begin a new transaction.
CLRSS;
}
#else
debugstr("Can't reflexively jam without SFD, FIFO, FIFOP, and P2LEDx definitions - try using telosb platform.");
- txdata(app,NOK,0);
+ txdata(CCSPI,NOK,0);
#endif
}
#ifdef FIFOP
//Has there been an overflow?
if((!FIFO)&&FIFOP){
- //debugstr("Clearing overflow");
+ debugstr("Clearing overflow");
CLRSS;
ccspitrans8(0x08); //SFLUSHRX
SETSS;
+ txdata(app,verb,0); //no packet
+ return;
}
//Is there a packet?
ccspitrans8(CCSPI_RXFIFO | 0x40);
//ccspitrans8(0x3F|0x40);
cmddata[0]=0xff; //to be replaced with length
- for(i=0;i<cmddata[0]+2;i++)
- cmddata[i]=ccspitrans8(0xde);
+
+
+ /* This reads too far on some CC2420 revisions, but on others it
+ works fine. It probably has to do with whether FIFO drops
+ before or after the SPI clocking.
+
+ A software fix is to reset the CC2420 between packets. This
+ works, but a better solution is desired.
+ */
+ //for(i=0;i<cmddata[0]+1;i++)
+ for(i=0;FIFO && i<0x80;i++)
+ cmddata[i]=ccspitrans8(0x00);
SETSS;
- //Flush buffer.
+ /* We used to flush the RX buffer after receive. No longer.
CLRSS;
ccspitrans8(0x08); //SFLUSHRX
SETSS;
-
+ */
//Only should transmit length of one more than the reported
// length of the frame, which holds the length byte:
- txdata(app,verb,cmddata[0]+1);
+ txdata(app,verb,i&0x7F);
}else{
//No packet.
txdata(app,verb,0);
//TODO disable AUTOCRC here again to go back to promiscous mode
//Turn off LED 2 (green) as signal
- PLED2DIR |= PLED2PIN;
- PLED2OUT |= PLED2PIN;
+ PLED2DIR |= PLED2PIN;
+ PLED2OUT |= PLED2PIN;
}
//TODO the firmware stops staying in this mode after a while, and stops jamming... need to find a fix.
#else