!GEN is now 1 by default.

[goodfet] / firmware / goodfet.c

diff --git a/firmware/goodfet.c b/firmware/goodfet.c
index 1e9b015..355ae00 100644 (file)
--- a/firmware/goodfet.c
+++ b/firmware/goodfet.c
@@ -27,13 +27,29 @@ void init(){
   msp430_init_uart();\r
   \r
   //DAC should be at full voltage if it exists.\r
-  #ifdef DAC12IR\r
+#ifdef DAC12IR\r
   //glitchvoltages(0xfff,0xfff);\r
   ADC12CTL0 = REF2_5V + REFON;                  // Internal 2.5V ref on\r
   for(i=0;i!=0xFFFF;i++) asm("nop");\r
   DAC12_0CTL = DAC12IR + DAC12AMP_5 + DAC12ENC; // Int ref gain 1\r
-  DAC12_0DAT = 0xFFF; //Max voltage\r
-  #endif\r
+  DAC12_0DAT = 0xFFF; //Max voltage 0xfff\r
+  DAC12_1CTL = DAC12IR + DAC12AMP_5 + DAC12ENC; // Int ref gain 1\r
+  DAC12_1DAT = 0x000; //Min voltage 0x000\r
+#endif\r
+  \r
+  /** FIXME\r
+      \r
+      This part is really ugly.  GSEL (P5.7) must be high to select\r
+      normal voltage, but a lot of applications light to swing it low\r
+      to be a nuissance.  To get around this, we assume that anyone\r
+      with a glitching FET will also have a DAC, then we set that DAC\r
+      to a high voltage.\r
+      \r
+      At some point, each target must be sanitized to show that it\r
+      doesn't clear P5OUT or P5DIR.\r
+  */\r
+  P5DIR|=BIT7; P5OUT=BIT7; //Normal Supply\r
+  //P5DIR&=~BIT7; //Glitch Supply\r
   \r
   //Enable Interrupts.\r
   //eint();\r