+/*! \file jtag.h
+ \author Travis Goodspeed
+ \brief JTAG handler functions.
+*/
#include <signal.h>
#include <io.h>
#include <iomacros.h>
+extern unsigned int drwidth;
+
+#define MSP430MODE 0
+#define MSP430XMODE 1
+#define MSP430X2MODE 2
+extern unsigned int jtag430mode;
+
// Generic Commands
+//! Shift n bytes.
+unsigned long jtagtransn(unsigned long word,
+ unsigned int bitcount);
+//! Shift the address width.
+unsigned long jtag_dr_shiftadr(unsigned long in);
//! Shift 8 bits of the IR.
unsigned char jtag_ir_shift8(unsigned char);
//! Shift 16 bits of the DR.
unsigned int jtag_dr_shift16(unsigned int);
+//! Shift 20 bits of the DR, MSP430 specific.
+unsigned long jtag_dr_shift20(unsigned long in);
//! Stop JTAG, release pins
void jtag_stop();
+//! Setup the JTAG pin directions.
void jtagsetup();
// JTAG430 Commands
//! Reset the TAP state machine, check the fuse.
void jtag430_resettap();
+//! Defined in jtag430asm.S
+void jtag430_tclk_flashpulses(int);
+
//High-level Macros follow
//! Write data to address.
void jtag430_writemem(unsigned int adr, unsigned int data);
#define SAVETCLK savedtclk=P5OUT&TCLK;
#define RESTORETCLK if(savedtclk) P5OUT|=TCLK; else P5OUT&=~TCLK
-//JTAG commands, bit-swapped
+//Replace every "CLRTCK SETTCK" with this.
+#define TCKTOCK CLRTCK,SETTCK
+
+
+//16-bit MSP430 JTAG commands, bit-swapped
+//Rewrite these with MSP430 prefix.
#define IR_CNTRL_SIG_16BIT 0xC8 // 0x13
#define IR_CNTRL_SIG_CAPTURE 0x28 // 0x14
#define IR_CNTRL_SIG_RELEASE 0xA8 // 0x15
// Bypass instruction
#define IR_BYPASS 0xFF // 0xFF
+//MSP430X2 unique
+#define IR_COREIP_ID 0xE8 // 0x17
+#define IR_DEVICE_ID 0xE1 // 0x87
+
+//MSP430 or MSP430X
+#define MSP430JTAGID 0x89
+//MSP430X2 only
+#define MSP430X2JTAGID 0x91
+
+//! Syncs a POR.
+unsigned int jtag430x2_syncpor();
+//! Executes an MSP430X2 POR
+unsigned int jtag430x2_por();
+//! Power-On Reset
+void jtag430_por();
+
+//JTAG commands
+#define JTAG_IR_SHIFT 0x80
+#define JTAG_DR_SHIFT 0x81
+#define JTAG_DR_SHIFT20 0x91
+
+
+//JTAG430 commands
+#define JTAG430_HALTCPU 0xA0
+#define JTAG430_RELEASECPU 0xA1
+#define JTAG430_SETINSTRFETCH 0xC1
+#define JTAG430_SETPC 0xC2
+#define JTAG430_SETREG 0xD2
+#define JTAG430_GETREG 0xD3
+#define JTAG430_WRITEMEM 0xE0
+#define JTAG430_WRITEFLASH 0xE1
+#define JTAG430_READMEM 0xE2
+#define JTAG430_ERASEFLASH 0xE3
+#define JTAG430_ERASECHECK 0xE4
+#define JTAG430_VERIFYMEM 0xE5
+#define JTAG430_BLOWFUSE 0xE6
+#define JTAG430_ISFUSEBLOWN 0xE7
+#define JTAG430_COREIP_ID 0xF0
+#define JTAG430_DEVICE_ID 0xF1