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jtagarm: added jtag_trans_many and supporting firmware and client functions/protocol...
[goodfet]
/
firmware
/
include
/
jtagarm7.h
diff --git
a/firmware/include/jtagarm7.h
b/firmware/include/jtagarm7.h
index
41ba258
..
74016a1
100644
(file)
--- a/
firmware/include/jtagarm7.h
+++ b/
firmware/include/jtagarm7.h
@@
-40,6
+40,9
@@
void jtagarm7tdmi_set_register(unsigned long reg, unsigned long val);
//! Get a 32-bit ARM register
unsigned long jtagarm7tdmi_get_register(unsigned long reg);
//! Get a 32-bit ARM register
unsigned long jtagarm7tdmi_get_register(unsigned long reg);
+//! Shift an arbitrary number of bits, using an array of uchars
+uint8_t* jtag_trans_many(uint8_t *word, uint8_t bitcount, enum eTransFlags flags);
+
// ARM7TDMI-specific pins
// DBGRQ - GoodFET Pin 8
#define DBGRQ TST
// ARM7TDMI-specific pins
// DBGRQ - GoodFET Pin 8
#define DBGRQ TST
@@
-102,9
+105,9
@@
The least significant bit of the instruction register is scanned in and scanned
//JTAGARM7TDMI commands
//JTAGARM7TDMI commands
-#define JTAGARM7_GET_REGISTER 0x8
7
-#define JTAGARM7_SET_REGISTER 0x8
8
-#define JTAGARM7_DEBUG_INSTR 0x8
9
+#define JTAGARM7_GET_REGISTER 0x8
d
+#define JTAGARM7_SET_REGISTER 0x8
e
+#define JTAGARM7_DEBUG_INSTR 0x8
f
// Really ARM specific stuff
#define JTAGARM7_SET_IR 0x90
#define JTAGARM7_WAIT_DBG 0x91
// Really ARM specific stuff
#define JTAGARM7_SET_IR 0x90
#define JTAGARM7_WAIT_DBG 0x91
@@
-113,7
+116,11
@@
The least significant bit of the instruction register is scanned in and scanned
#define JTAGARM7_SCANCHAIN1 0x94
#define JTAGARM7_EICE_READ 0x95
#define JTAGARM7_EICE_WRITE 0x96
#define JTAGARM7_SCANCHAIN1 0x94
#define JTAGARM7_EICE_READ 0x95
#define JTAGARM7_EICE_WRITE 0x96
+#define JTAGARM7_IR_SIZE 0x9f
+#define JTAGARM7_SCAN_N_SIZE 0x9e
+#define JTAGARM_SCAN1_MANY 0x9d
+#define JTAG_DR_SHIFT_MANY 0x9c
// for deeper understanding, read the instruction cycle timing section of:
// http://www.atmel.com/dyn/resources/prod_documents/DDI0029G_7TDMI_R3_trm.pdf
// for deeper understanding, read the instruction cycle timing section of:
// http://www.atmel.com/dyn/resources/prod_documents/DDI0029G_7TDMI_R3_trm.pdf
@@
-156,8
+163,9
@@
The least significant bit of the instruction register is scanned in and scanned
#define JTAG_ARM7TDMI_DBG_IFEN 4
#define JTAG_ARM7TDMI_DBG_cgenL 8
#define JTAG_ARM7TDMI_DBG_TBIT 16
#define JTAG_ARM7TDMI_DBG_IFEN 4
#define JTAG_ARM7TDMI_DBG_cgenL 8
#define JTAG_ARM7TDMI_DBG_TBIT 16
-
extern app_t const jtagarm7_app;
extern app_t const jtagarm7_app;
+extern unsigned char g_jtag_ir_size;
+extern unsigned char g_jtagarm_scan_n_bitsize;
#endif // JTAGARM7_H
#endif // JTAGARM7_H