jtagtransn reworked. testing looks good so far.

[goodfet] / firmware / include / jtagarm7tdmi.h

diff --git a/firmware/include/jtagarm7tdmi.h b/firmware/include/jtagarm7tdmi.h
index c17ac93..37960fe 100644 (file)
--- a/firmware/include/jtagarm7tdmi.h
+++ b/firmware/include/jtagarm7tdmi.h
@@ -16,6 +16,7 @@
 
 
 unsigned char current_chain;
+unsigned char current_dbgstate = -1;
 unsigned char last_halt_debug_state = -1;
 unsigned long last_halt_pc = -1;
 unsigned long count_dbgspd_instr_since_debug = 0;
@@ -63,6 +64,10 @@ unsigned long jtagarm7tdmi_idcode();
 unsigned char jtagarm7tdmi_bypass();
 //!  Connect the appropriate scan chain to TDO/TDI
 unsigned long jtagarm7tdmi_scan_intest(int n);
+//!  Set a 32-bit ARM register
+void jtagarm7tdmi_set_register(unsigned long reg, unsigned long val);
+//!  Get a 32-bit ARM register
+unsigned long jtagarm7tdmi_get_register(unsigned long reg);
 
 // ARM7TDMI-specific pins
 // DBGRQ - GoodFET Pin 8
@@ -125,14 +130,6 @@ The least significant bit of the instruction register is scanned in and scanned
 #define EICE_WP1CTRLMASK                21
 
 
-#define NOEND 0
-#define END 1
-#define MSB 0
-#define LSB 1
-#define NORETIDLE 0
-#define RETIDLE 1
-
-
 //JTAGARM7TDMI commands
 #define JTAGARM7TDMI_GET_DEBUG_CTRL       0x80
 #define JTAGARM7TDMI_SET_DEBUG_CTRL       0x81
@@ -165,30 +162,36 @@ The least significant bit of the instruction register is scanned in and scanned
 #define JTAGARM7TDMI_SET_SPSR             0x9b
 #define JTAGARM7TDMI_SET_MODE_THUMB       0x9c
 #define JTAGARM7TDMI_SET_MODE_ARM         0x9d
+#define JTAGARM7TDMI_SET_IR               0x9e
+#define JTAGARM7TDMI_WAIT_DBG             0x9f
+#define JTAGARM7TDMI_SHIFT_DR             0xa0
+#define JTAGARM7TDMI_SETWATCH0            0xa1
+#define JTAGARM7TDMI_SETWATCH1            0xa2
+#define JTAGARM7TDMI_CHAIN0               0xa3
 
 
 // for deeper understanding, read the instruction cycle timing section of: 
 //      http://www.atmel.com/dyn/resources/prod_documents/DDI0029G_7TDMI_R3_trm.pdf
 #define EXECNOPARM                  0xe1a00000L
 #define ARM_INSTR_NOP               0xe1a00000L
-#define ARM_INSTR_STR_Rx_r14        0xe58e0000L // from atmel docs
-//#define ARM_INSTR_STR_Rx_r14        0xe5800000L // set both src and dest reg in code
+#define ARM_INSTR_BX_R0             0xe12fff10L
+#define ARM_INSTR_STR_Rx_r14        0xe58f0000L // from atmel docs
 #define ARM_READ_REG                ARM_INSTR_STR_Rx_r14
-#define ARM_INSTR_LDR_Rx_r14        0xe59e0000L // from atmel docs
-//#define ARM_INSTR_LDR_Rx_r14        0xe5900000L // set both src and dest reg in code
+#define ARM_INSTR_LDR_Rx_r14        0xe59f0000L // from atmel docs
 #define ARM_WRITE_REG               ARM_INSTR_LDR_Rx_r14
 #define ARM_INSTR_LDR_R1_r0_4       0xe4901004L
 #define ARM_READ_MEM                ARM_INSTR_LDR_R1_r0_4
-#define ARM_INSTR_MRS_R0_CPSR       0xf10f0000L
+#define ARM_INSTR_STR_R1_r0_4       0xe4801004L
+#define ARM_WRITE_MEM               ARM_INSTR_STR_R1_r0_4
+#define ARM_INSTR_MRS_R0_CPSR       0xe10f0000L
 #define ARM_INSTR_MSR_cpsr_cxsf_R0  0xe12ff000L
 #define ARM_INSTR_STMIA_R14_r0_rx   0xE88E0000L      // add up to 65k to indicate which registers...
-#define ARM_STORE_MULTIPLE          ARM_INSTR_STMIA_R14_r0-rx
-#define ARM_INSTR_SKANKREGS1        0xE88E00ffL
-#define ARM_INSTR_SKANKREGS2        0xE88Eff00L
-#define ARM_INSTR_CLOBBEREGS        0xE89EffffL
+#define ARM_STORE_MULTIPLE          ARM_INSTR_STMIA_R14_r0_rx
+#define ARM_INSTR_SKANKREGS         0xE88F7fffL
+#define ARM_INSTR_CLOBBEREGS        0xE89F7fffL
 
-#define ARM_INSTR_B_PC              0xea000000L
-#define ARM_INSTR_BX_PC             0xe1200010L      // need to set r0 to the desired address
+#define ARM_INSTR_B_IMM             0xea000000L
+#define ARM_INSTR_BX_PC             0xe12fff10L      // need to set r0 to the desired address
 #define THUMB_INSTR_STR_R0_r0       0x60006000L
 #define THUMB_INSTR_MOV_R0_PC       0x46b846b8L
 #define THUMB_INSTR_BX_PC           0x47784778L