w00t! jtagarm7 committed and included in build.

[goodfet] / firmware / include / jtagarm7tdmi.h

diff --git a/firmware/include/jtagarm7tdmi.h b/firmware/include/jtagarm7tdmi.h
index 43ea82c..fe2bc41 100644 (file)
--- a/firmware/include/jtagarm7tdmi.h
+++ b/firmware/include/jtagarm7tdmi.h
@@ -49,7 +49,7 @@ unsigned long jtagarm7tdmi_writeflash(unsigned long adr, unsigned long data);
 
 
 //! Start JTAG
 
 
 //! Start JTAG

-unsigned long jtagarm7tdmi_start(void);
+void jtagarm7tdmi_start(void);

 //! Reset TAP State Machine
 void jtagarm7tdmi_resettap();
 
 //! Reset TAP State Machine
 void jtagarm7tdmi_resettap();
 


@@ -130,46 +130,18 @@ The least significant bit of the instruction register is scanned in and scanned
 #define EICE_WP1CTRLMASK                21
 
 
 #define EICE_WP1CTRLMASK                21
 
 

-#define NOEND 0
-#define END 1
-#define MSB 0
-#define LSB 1
-#define NORETIDLE 0
-#define RETIDLE 1
-
-

 //JTAGARM7TDMI commands
 //JTAGARM7TDMI commands

-#define JTAGARM7TDMI_GET_DEBUG_CTRL       0x80
-#define JTAGARM7TDMI_SET_DEBUG_CTRL       0x81
-#define JTAGARM7TDMI_GET_PC               0x82
-#define JTAGARM7TDMI_SET_PC               0x83
-#define JTAGARM7TDMI_GET_CHIP_ID          0x84
-#define JTAGARM7TDMI_GET_DEBUG_STATE      0x85
-#define JTAGARM7TDMI_GET_WATCHPOINT       0x86
-#define JTAGARM7TDMI_SET_WATCHPOINT       0x87
-#define JTAGARM7TDMI_GET_REGISTER         0x88
-#define JTAGARM7TDMI_SET_REGISTER         0x89
-#define JTAGARM7TDMI_GET_REGISTERS        0x8a
-#define JTAGARM7TDMI_SET_REGISTERS        0x8b
-#define JTAGARM7TDMI_HALTCPU              0x8c
-#define JTAGARM7TDMI_RELEASECPU           0x8d
-#define JTAGARM7TDMI_DEBUG_INSTR          0x8e
-#define JTAGARM7TDMI_STEP_INSTR           0x8f
-#define JTAGARM7TDMI_WRITEMEM             0x90
-#define JTAGARM7TDMI_READMEM              0x91
-#define JTAGARM7TDMI_WRITE_FLASH_PAGE     0x92
-#define JTAGARM7TDMI_READ_FLASH_PAGE      0x93
-#define JTAGARM7TDMI_MASS_ERASE_FLASH     0x94
-#define JTAGARM7TDMI_PROGRAM_FLASH        0x95
-#define JTAGARM7TDMI_LOCKCHIP             0x96
-#define JTAGARM7TDMI_CHIP_ERASE           0x97
+#define JTAGARM7_GET_REGISTER               0x87
+#define JTAGARM7_SET_REGISTER               0x88
+#define JTAGARM7_DEBUG_INSTR                0x89

 // Really ARM specific stuff
 // Really ARM specific stuff

-#define JTAGARM7TDMI_GET_CPSR             0x98
-#define JTAGARM7TDMI_SET_CPSR             0x99
-#define JTAGARM7TDMI_GET_SPSR             0x9a
-#define JTAGARM7TDMI_SET_SPSR             0x9b
-#define JTAGARM7TDMI_SET_MODE_THUMB       0x9c
-#define JTAGARM7TDMI_SET_MODE_ARM         0x9d
+#define JTAGARM7_SET_IR                     0x90
+#define JTAGARM7_WAIT_DBG                   0x91
+#define JTAGARM7_SHIFT_DR                   0x92
+#define JTAGARM7_CHAIN0                     0x93
+#define JTAGARM7_SCANCHAIN1                 0x94
+#define JTAGARM7_EICE_READ                  0x95
+#define JTAGARM7_EICE_WRITE                 0x96

 
 
 // for deeper understanding, read the instruction cycle timing section of: 
 
 
 // for deeper understanding, read the instruction cycle timing section of: 


@@ -188,12 +160,12 @@ The least significant bit of the instruction register is scanned in and scanned
 #define ARM_INSTR_MRS_R0_CPSR       0xe10f0000L
 #define ARM_INSTR_MSR_cpsr_cxsf_R0  0xe12ff000L
 #define ARM_INSTR_STMIA_R14_r0_rx   0xE88E0000L      // add up to 65k to indicate which registers...
 #define ARM_INSTR_MRS_R0_CPSR       0xe10f0000L
 #define ARM_INSTR_MSR_cpsr_cxsf_R0  0xe12ff000L
 #define ARM_INSTR_STMIA_R14_r0_rx   0xE88E0000L      // add up to 65k to indicate which registers...

-#define ARM_STORE_MULTIPLE          ARM_INSTR_STMIA_R14_r0-rx
+#define ARM_STORE_MULTIPLE          ARM_INSTR_STMIA_R14_r0_rx

 #define ARM_INSTR_SKANKREGS         0xE88F7fffL
 #define ARM_INSTR_CLOBBEREGS        0xE89F7fffL
 
 #define ARM_INSTR_SKANKREGS         0xE88F7fffL
 #define ARM_INSTR_CLOBBEREGS        0xE89F7fffL
 

-#define ARM_INSTR_B_PC              0xea000000L
-#define ARM_INSTR_BX_PC             0xe1200010L      // need to set r0 to the desired address
+#define ARM_INSTR_B_IMM             0xea000000L
+#define ARM_INSTR_BX_PC             0xe12fff10L      // need to set r0 to the desired address

 #define THUMB_INSTR_STR_R0_r0       0x60006000L
 #define THUMB_INSTR_MOV_R0_PC       0x46b846b8L
 #define THUMB_INSTR_BX_PC           0x47784778L
 #define THUMB_INSTR_STR_R0_r0       0x60006000L
 #define THUMB_INSTR_MOV_R0_PC       0x46b846b8L
 #define THUMB_INSTR_BX_PC           0x47784778L