Proper self-calibration of the DCO.

[goodfet] / firmware / lib / msp430x2618.c

diff --git a/firmware/lib/msp430x2618.c b/firmware/lib/msp430x2618.c
index ac17e0d..587d6e2 100644 (file)
--- a/firmware/lib/msp430x2618.c
+++ b/firmware/lib/msp430x2618.c
@@ -1,7 +1,6 @@
 //! MSP430F2618 clock and I/O definitions
 
-// Ought to be portable to other 2xx chips.
-// 2274 looks particularly appealing.
+// Included by other 2xx ports, such as the 2274.
 
 #include "platform.h"
 
@@ -9,7 +8,6 @@
 #include <io.h>
 #include <iomacros.h>
 
-
 //! Receive a byte.
 unsigned char serial_rx(){
   char c;
@@ -49,23 +47,28 @@ void serial1_tx(unsigned char x){
 //! Set the baud rate.
 void setbaud(unsigned char rate){
   
-  //http://mspgcc.sourceforge.net/baudrate.html
+  //Table 15-4, page 481 of 2xx Family Guide
   switch(rate){
   case 1://9600 baud
-    
+    UCA0BR1 = 0x06;
+    UCA0BR0 = 0x82;
     break;
   case 2://19200 baud
-    
+    UCA0BR1 = 0x03;
+    UCA0BR0 = 0x41;
     break;
   case 3://38400 baud
-    
+    UCA0BR1 = 0xa0;
+    UCA0BR0 = 0x01;
     break;
   case 4://57600 baud
-    
+    UCA0BR1 = 0x1d;
+    UCA0BR0 = 0x01;
     break;
   default:
   case 5://115200 baud
-    
+    UCA0BR0 = 0x8a;
+    UCA0BR1 = 0x00;
     break;
   }
 }
@@ -73,62 +76,103 @@ void setbaud(unsigned char rate){
 //! Set the baud rate of the second uart.
 void setbaud1(unsigned char rate){
   
-  //http://mspgcc.sourceforge.net/baudrate.html
-  switch(rate){
-  case 1://9600 baud
-    
-    break;
-  case 2://19200 baud
-    
-    break;
-  case 3://38400 baud
-    
-    break;
-  case 4://57600 baud
-    
-    break;
-  default:
-  case 5://115200 baud
-    
-    break;
-  }
 }
 
-
-
-//19200
-#define BAUD0EN 0x1b
-#define BAUD1EN 0x00
-
+#define BAUD0EN 0x41
+#define BAUD1EN 0x03
 
 void msp430_init_uart(){
-
-  // Serial on P3.4, P3.5                                                                                                                                                 
+  
+  // Serial on P3.4, P3.5
   P3SEL |= BIT4 + BIT5;
   P3DIR |= BIT4;
-
-  //UCA0CTL1 |= UCSWRST;                    /* disable UART */                                                                                                            
-
+  
+  //UCA0CTL1 |= UCSWRST;                    /* disable UART */
+  
   UCA0CTL0 = 0x00;
-  //UCA0CTL0 |= UCMSB ;                                                                                                                                                   
-  UCA0CTL1 |= UCSSEL_2;                     // SMCLK                                                                                                                      
-  UCA0BR0 = BAUD0EN;                        // 115200                                                                                                                     
-  UCA0BR1 = BAUD1EN;
-  UCA0MCTL = 0;                             // Modulation UCBRSx = 5                                                                                                      
-  UCA0CTL1 &= ~UCSWRST;                     // **Initialize USCI state machine**                                                                                          
-
-
-  //Leave this commented!                                                                                                                                                 
-  //Interrupt is handled by target code, not by bootloader.                                                                                                               
-  //IE2 |= UCA0RXIE;         
+  //UCA0CTL0 |= UCMSB ;
+  
+  UCA0CTL1 |= UCSSEL_2;                     // SMCLK
+  
+  //UCA0BR0 = BAUD0EN;                        // 115200
+  //UCA0BR1 = BAUD1EN;
+  setbaud(5);//default baud, 115200
+  
+  UCA0MCTL = 0;                             // Modulation UCBRSx = 5
+  UCA0CTL1 &= ~UCSWRST;                     // **Initialize USCI state machine**
+  
+  
+  //Leave this commented!
+  //Interrupt is handled by target code, not by bootloader.
+  //IE2 |= UCA0RXIE;
+}
 
+/* Info Flash Values
+CALDCO_16MHZ 0xdc CALBC1_16MHZ 0x8e   2274-000.txt
+CALDCO_16MHZ 0x74 CALBC1_16MHZ 0x8f   2618-000.txt
+CALDCO_16MHZ 0x6c CALBC1_16MHZ 0x8f   2618-001.txt
+CALDCO_16MHZ 0x97 CALBC1_16MHZ 0x8f   2618-002.txt
+CALDCO_16MHZ 0x6c CALBC1_16MHZ 0x8f   2618-003.txt
+CALDCO_16MHZ 0x95 CALBC1_16MHZ 0x8f   2618-004.txt
+CALDCO_16MHZ 0xcc CALBC1_16MHZ 0x8e   2618-005.txt
+CALDCO_16MHZ 0x87 CALBC1_16MHZ 0x8f   2618-006.txt
+CALDCO_16MHZ 0x96 CALBC1_16MHZ 0x8f   2619-001.txt
+*/
+
+//! Initialization is correct.
+void msp430_init_dco_done(){
+  char *choice=(char *) 0x200; //First word of RAM.
+  choice[0]--;
 }
 
-//external resistor
-#define DCOR 1
+//! Initialize the MSP430 clock.
 void msp430_init_dco() {
-  BCSCTL1 = CALBC1_16MHZ;
-  DCOCTL = CALDCO_16MHZ;  
+  int i=1000;
+  char *choice=(char *) 0x200; //First word of RAM.
+  #ifdef __MSP430_HAS_PORT8__
+  P8SEL = 0; // disable XT2 on P8.7/8
+  #endif
+  
+  if(CALBC1_16MHZ!=0xFF){
+    //Info is intact, use it.
+    BCSCTL1 = CALBC1_16MHZ;
+    DCOCTL = CALDCO_16MHZ;
+  }else{
+    /*
+      Info is missing, guess at a good value.
+      
+      For now, the choice doesn't jump backward after a successful
+      connection.  For that reason, keep this list as small as possible.
+      Future revisions will subtract one from choice[0] after a successful
+      connection, keeping choice[1] as the target.
+    */
+      
+    #define CHOICES 4
+    DCOCTL = 0x00; //clear DCO
+    switch(choice[0]++%CHOICES){
+    default:
+    case 0:
+      BCSCTL1 = 0x8f;   //CALBC1_16MHZ at 0x10f9
+      DCOCTL = 0x83;    //CALDCO_16MHZ at 0x10f8
+      break;
+    case 1:
+      BCSCTL1 = 0x8f;
+      DCOCTL = 0x95;
+      break;
+    case 2:
+      BCSCTL1 = 0x8f;
+      DCOCTL = 0x6c;
+      break;
+    case 3:
+      BCSCTL1 = 0x8e;
+      DCOCTL = 0xdc;
+      break;
+    }
+  }
+  
+  //Minor delay.
+  while(i--);
+  
   return;
 }