Fixed the P8SEL bug in msp430x2618.c, as the port doesn't exist on the 2274.

[goodfet] / firmware / lib / msp430x2618.c

diff --git a/firmware/lib/msp430x2618.c b/firmware/lib/msp430x2618.c
index 814c8ef..6ad6f9c 100644 (file)
--- a/firmware/lib/msp430x2618.c
+++ b/firmware/lib/msp430x2618.c
@@ -126,8 +126,24 @@ void msp430_init_uart(){
   //IE2 |= UCA0RXIE;
 }
 
+/* Info Flash Values
+CALDCO_16MHZ 0xdc CALBC1_16MHZ 0x8e   2274-000.txt
+CALDCO_16MHZ 0x74 CALBC1_16MHZ 0x8f   2618-000.txt
+CALDCO_16MHZ 0x6c CALBC1_16MHZ 0x8f   2618-001.txt
+CALDCO_16MHZ 0x97 CALBC1_16MHZ 0x8f   2618-002.txt
+CALDCO_16MHZ 0x6c CALBC1_16MHZ 0x8f   2618-003.txt
+CALDCO_16MHZ 0x95 CALBC1_16MHZ 0x8f   2618-004.txt
+CALDCO_16MHZ 0xcc CALBC1_16MHZ 0x8e   2618-005.txt
+CALDCO_16MHZ 0x87 CALBC1_16MHZ 0x8f   2618-006.txt
+CALDCO_16MHZ 0x96 CALBC1_16MHZ 0x8f   2619-001.txt
+*/
+
 //! Initialize the MSP430 clock.
 void msp430_init_dco() {
+  #ifdef __MSP430_HAS_PORT8__
+  P8SEL = 0; // disable XT2 on P8.7/8
+  #endif
+  
   if(CALBC1_16MHZ!=0xFF){
     //Info is intact, use it.
     BCSCTL1 = CALBC1_16MHZ;
@@ -138,8 +154,14 @@ void msp430_init_dco() {
     default:
     case 0x6ff2:        //f26f, the MSP430F2618
       DCOCTL = 0x00;
-      BCSCTL1 = 0x8f;   //CALBC1_16MHZ at 0x10f9
-      DCOCTL = 0x7f;    //CALDCO_16MHZ at 0x10f8
+      #ifndef DCOVAL
+      #define DCOVAL 0x8f
+      #endif
+      BCSCTL1 = DCOVAL;   //CALBC1_16MHZ at 0x10f9
+      /** Observed DCOCTL values:
+         2618: 7f, 97
+      */
+      DCOCTL = 0x83;    //CALDCO_16MHZ at 0x10f8
       break;
     }
   }