X-Git-Url: http://git.rot13.org/?p=goodfet;a=blobdiff_plain;f=client%2FGoodFETARM7.py;h=0864cb2019713a7138923945018ad66424b34f1d;hp=21f4fe7438d46276326d7838ec094dabd1c23a4e;hb=2dcd81fd2345fd3839a35f75f8fffcf79e359a5e;hpb=46911acb1c879cf7f43f2ac0ae56478a1b4fee24

diff --git a/client/GoodFETARM7.py b/client/GoodFETARM7.py
index 21f4fe7..0864cb2 100644
--- a/client/GoodFETARM7.py
+++ b/client/GoodFETARM7.py
@@ -1,8 +1,6 @@
 #!/usr/bin/env python
 # GoodFET ARM Client Library
 # 
-#
-# Good luck with alpha / beta code.
 # Contributions and bug reports welcome.
 #
 # todo:
@@ -10,15 +8,8 @@
 #  * ensure correct PC handling
 #  * flash manipulation (probably need to get the specific chip for this one)
 #  * set security (chip-specific)
-#  * -ancilary/faster- ldm/stm versions of memory access  (had trouble in past, possibly also due to haphazard abuse of DCLK)
-#  
-# fixme now stuff:
-#  * thumb mode get/set_register    - DONE!
-#  * thumb to arm mode              - DONE!
-#  * rethink the whole python/c trade-off for cross-python session debugging
 
 import sys, binascii, struct, time
-import atlasutils.smartprint as asp
 from GoodFET import GoodFET
 from intelhex import IntelHex
 
@@ -40,7 +31,7 @@ OK    = 0x7F
 IR_SHIFT =                  0x80
 DR_SHIFT =                  0x81
 RESETTAP =                  0x82
-RESETTARGET =               0x86
+RESETTARGET =               0x83
 GET_REGISTER =              0x87
 SET_REGISTER =              0x88
 DEBUG_INSTR =               0x89
@@ -251,10 +242,10 @@ class GoodFETARM(GoodFET):
         return retval
     def ARMidentstr(self):
         ident=self.ARMident()
-        ver     = ident >> 28
-        partno  = (ident >> 12) & 0x10
-        mfgid   = ident & 0xfff
-        return "mfg: %x\npartno: %x\nver: %x\n(%x)" % (ver, partno, mfgid, ident); 
+        ver     = (ident >> 28)
+        partno  = (ident >> 12) & 0xffff
+        mfgid   = (ident >> 1)  & 0x7ff
+        return "Chip IDCODE: 0x%x\n\tver: %x\n\tpartno: %x\n\tmfgid: %x\n" % (ident, ver, partno, mfgid); 
     def ARMeice_write(self, reg, val):
         data = chop(val,4)
         data.extend([reg])
@@ -313,9 +304,9 @@ class GoodFETARM(GoodFET):
         """Set ARM Registers"""
         for x in xrange(15):
           if (1<<x) & mask:
-            self.ARMset_register(x,regs.pop())
+            self.ARMset_register(x,regs.pop(0))
         if (1<<15) & mask:                      # make sure we set the "static" version of PC or changes will be lost
-          self.ARMsetPC(regs.pop())
+          self.ARMsetPC(regs.pop(0))
     def ARMdebuginstr(self,instr,bkpt):
         if type (instr) == int or type(instr) == long:
             instr = struct.pack("<L", instr)
@@ -323,7 +314,7 @@ class GoodFETARM(GoodFET):
         instr.extend([bkpt])
         self.writecmd(0x13,DEBUG_INSTR,len(instr),instr)
         return (self.data)
-    def ARM_nop(self, bkpt):
+    def ARM_nop(self, bkpt=0):
         if self.status() & DBG_TBIT:
             return self.ARMdebuginstr(THUMB_INSTR_NOP, bkpt)
         return self.ARMdebuginstr(ARM_INSTR_NOP, bkpt)
@@ -414,7 +405,7 @@ class GoodFETARM(GoodFET):
             print hex(self.ARMget_register(15))
             print hex(self.ARMchain0(self.storedPC,self.flags)[0])
             self.ARMdebuginstr(THUMB_INSTR_B_IMM | (0x7fc07fc),0)
-            self.ARM_nop()
+            self.ARM_nop(0)
             self.ARMrestart()
 
 
@@ -504,9 +495,11 @@ class GoodFETARM(GoodFET):
         WARNING: Addresses must be word-aligned!
         """
         regs = self.ARMget_registers()
+        self.ARMset_registers([0xdeadbeef for x in xrange(14)], 0xe)
         output = []
         count = wordcount
         while (wordcount > 0):
+            if (wordcount%64 == 0):  sys.stderr.write(".")
             count = (wordcount, 0xe)[wordcount>0xd]
             bitmask = LDM_BITMASKS[count]
             self.ARMset_register(14,adr)
@@ -518,9 +511,37 @@ class GoodFETARM(GoodFET):
             output.extend([self.ARMget_register(x) for x in xrange(count)])
             wordcount -= count
             adr += count*4
-            print hex(adr)
+            #print hex(adr)
         # FIXME: handle the rest of the wordcount here.
+        self.ARMset_registers(regs,0xe)
         return output
+    def ARMreadStream(self, adr, bytecount):
+        data = [struct.unpack("<L", x) for x in self.ARMreadChunk(adr, (bytecount-1/4)+1)]
+        return "".join(data)[:bytecount]
+        
+    def ARMwriteChunk(self, adr, wordarray):         
+        """ Only works in ARM mode currently
+        WARNING: Addresses must be word-aligned!
+        """
+        regs = self.ARMget_registers()
+        wordcount = len(wordarray)
+        while (wordcount > 0):
+            if (wordcount%64 == 0):  sys.stderr.write(".")
+            count = (wordcount, 0xe)[wordcount>0xd]
+            bitmask = LDM_BITMASKS[count]
+            self.ARMset_register(14,adr)
+            #print len(wordarray),bin(bitmask)
+            self.ARMset_registers(wordarray[:count],bitmask)
+            self.ARM_nop(1)
+            self.ARMdebuginstr(ARM_INSTR_STMIA_R14_r0_rx | bitmask ,0)
+            #FIXME: do we need the extra nop here?
+            self.ARMrestart()
+            self.ARMwaitDBG()
+            wordarray = wordarray[count:]
+            wordcount -= count
+            adr += count*4
+            #print hex(adr)
+        # FIXME: handle the rest of the wordcount here.
     def ARMwriteMem(self, adr, wordarray):
         r0 = self.ARMget_register(0);        # store R0 and R1
         r1 = self.ARMget_register(1);
@@ -536,7 +557,7 @@ class GoodFETARM(GoodFET):
             self.ARM_nop(0)
             self.ARMrestart()
             self.ARMwaitDBG()
-            print hex(self.ARMget_register(1))
+            print >>sys.stderr,hex(self.ARMget_register(1))
         self.ARMset_register(1, r1);       # restore R0 and R1 
         self.ARMset_register(0, r0);
 
@@ -552,22 +573,24 @@ class GoodFETARM(GoodFET):
                   0x02 : "force dbgrq",
                   0x01 : "force dbgack"
                   }
-                  
+    def ARMresettarget(self, delay=10):
+        return self.writecmd(0x13,RESETTARGET,2, [ delay&0xff, (delay>>8)&0xff ] )
     def ARMchain0(self, address, bits=0x819684c054, data=0):
         bulk = chop(address,4)
         bulk.extend(chop(bits,8))
         bulk.extend(chop(data,4))
-        print (repr(bulk))
+        print >>sys.stderr,(repr(bulk))
         self.writecmd(0x13,CHAIN0,16,bulk)
         d1,b1,a1 = struct.unpack("<LQL",self.data)
         return (a1,b1,d1)
     def start(self):
         """Start debugging."""
         self.writecmd(0x13,START,0,self.data)
+        print >>sys.stderr,"Identifying Target:"
         ident=self.ARMidentstr()
-        print "Target identifies as %s." % ident
-        print "Debug Status: %s." % self.statusstr()
-        #print "System State: %x." % self.ARMget_regCPSRstr()
+        print >>sys.stderr,ident
+        print >>sys.stderr,"Debug Status:\t%s\n" % self.statusstr()
+
     def stop(self):
         """Stop debugging."""
         self.writecmd(0x13,STOP,0,self.data)