X-Git-Url: http://git.rot13.org/?p=goodfet;a=blobdiff_plain;f=client%2FGoodFETARM7.py;h=206c82028358643494576edc875ca6e745e7f623;hp=be1c9539db40021379214c5167dda02e8231eb35;hb=44e1187885bbf7caa7cafccf7cc41d0ec3963721;hpb=6ec4512553ac11e9893437fd80ab21992f0ab4f5 diff --git a/client/GoodFETARM7.py b/client/GoodFETARM7.py index be1c953..206c820 100644 --- a/client/GoodFETARM7.py +++ b/client/GoodFETARM7.py @@ -1,8 +1,6 @@ #!/usr/bin/env python # GoodFET ARM Client Library # -# -# Good luck with alpha / beta code. # Contributions and bug reports welcome. # # todo: @@ -10,15 +8,8 @@ # * ensure correct PC handling # * flash manipulation (probably need to get the specific chip for this one) # * set security (chip-specific) -# * -ancilary/faster- ldm/stm versions of memory access (had trouble in past, possibly also due to haphazard abuse of DCLK) -# -# fixme now stuff: -# * thumb mode get/set_register -# * thumb to arm mode -# * rethink the whole python/c trade-off for cross-python session debugging import sys, binascii, struct, time -import atlasutils.smartprint as asp from GoodFET import GoodFET from intelhex import IntelHex @@ -40,7 +31,7 @@ OK = 0x7F IR_SHIFT = 0x80 DR_SHIFT = 0x81 RESETTAP = 0x82 -RESETTARGET = 0x86 +RESETTARGET = 0x83 GET_REGISTER = 0x87 SET_REGISTER = 0x88 DEBUG_INSTR = 0x89 @@ -131,9 +122,12 @@ ARM_INSTR_LDR_R1_r0_4 = 0xe4901004L ARM_READ_MEM = ARM_INSTR_LDR_R1_r0_4 ARM_INSTR_STR_R1_r0_4 = 0xe4801004L ARM_WRITE_MEM = ARM_INSTR_STR_R1_r0_4 +ARM_INSTR_STRB_R1_r0_1 = 0xe4c01001L +ARM_WRITE_MEM_BYTE = ARM_INSTR_STRB_R1_r0_1 ARM_INSTR_MRS_R0_CPSR = 0xe10f0000L ARM_INSTR_MSR_cpsr_cxsf_R0 =0xe12ff000L -ARM_INSTR_STMIA_R14_r0_rx = 0xE88E0000L # add up to 65k to indicate which registers... +ARM_INSTR_STMIA_R14_r0_rx = 0xE88e0000L # add up to 65k to indicate which registers... +ARM_INSTR_LDMIA_R14_r0_rx = 0xE89e0000L # add up to 65k to indicate which registers... ARM_STORE_MULTIPLE = ARM_INSTR_STMIA_R14_r0_rx ARM_INSTR_SKANKREGS = 0xE88F7fffL ARM_INSTR_CLOBBEREGS = 0xE89F7fffL @@ -183,6 +177,12 @@ DBGCTRLBITS = { 1<>sys.stderr,(strng) @@ -244,10 +244,10 @@ class GoodFETARM(GoodFET): return retval def ARMidentstr(self): ident=self.ARMident() - ver = ident >> 28 - partno = (ident >> 12) & 0x10 - mfgid = ident & 0xfff - return "mfg: %x\npartno: %x\nver: %x\n(%x)" % (ver, partno, mfgid, ident); + ver = (ident >> 28) + partno = (ident >> 12) & 0xffff + mfgid = (ident >> 1) & 0x7ff + return "Chip IDCODE: 0x%x\n\tver: %x\n\tpartno: %x\n\tmfgid: %x\n" % (ident, ver, partno, mfgid); def ARMeice_write(self, reg, val): data = chop(val,4) data.extend([reg]) @@ -289,7 +289,7 @@ class GoodFETARM(GoodFET): self.storedPC = val def ARMget_register(self, reg): """Get an ARM's Register""" - self.writecmd(0x13,GET_REGISTER,1,[reg&0xff]) + self.writecmd(0x13,GET_REGISTER,1,[reg&0xf]) retval = struct.unpack(" 0): + if (wordcount%64 == 0): sys.stderr.write(".") + count = (wordcount, 0xe)[wordcount>0xd] + bitmask = LDM_BITMASKS[count] + self.ARMset_register(14,adr) + self.ARM_nop(1) + self.ARMdebuginstr(ARM_INSTR_LDMIA_R14_r0_rx | bitmask ,0) + #FIXME: do we need the extra nop here? + self.ARMrestart() + self.ARMwaitDBG() + output.extend([self.ARMget_register(x) for x in xrange(count)]) + wordcount -= count + adr += count*4 + #print hex(adr) + # FIXME: handle the rest of the wordcount here. + self.ARMset_registers(regs,0xe) + return output + def ARMreadStream(self, adr, bytecount): + data = [struct.unpack(" 0): + if (wordcount%64 == 0): sys.stderr.write(".") + count = (wordcount, 0xe)[wordcount>0xd] + bitmask = LDM_BITMASKS[count] + self.ARMset_register(14,adr) + #print len(wordarray),bin(bitmask) + self.ARMset_registers(wordarray[:count],bitmask) + self.ARM_nop(1) + self.ARMdebuginstr(ARM_INSTR_STMIA_R14_r0_rx | bitmask ,0) + #FIXME: do we need the extra nop here? + self.ARMrestart() + self.ARMwaitDBG() + wordarray = wordarray[count:] + wordcount -= count + adr += count*4 + #print hex(adr) + # FIXME: handle the rest of the wordcount here. + def ARMwriteMem(self, adr, wordarray, instr=ARM_WRITE_MEM): r0 = self.ARMget_register(0); # store R0 and R1 r1 = self.ARMget_register(1); #print >>sys.stderr,("CPSR:\t%x"%self.ARMget_regCPSR()) @@ -495,13 +555,16 @@ class GoodFETARM(GoodFET): self.ARMset_register(1, word); # write address into R0 self.ARM_nop(0) self.ARM_nop(1) - self.ARMdebuginstr(ARM_WRITE_MEM, 0); # push STR R1, [R0], #4 into instruction pipeline (autoincrements for consecutive writes) + self.ARMdebuginstr(instr, 0); # push STR R1, [R0], #4 into instruction pipeline (autoincrements for consecutive writes) self.ARM_nop(0) self.ARMrestart() self.ARMwaitDBG() - print hex(self.ARMget_register(1)) + print >>sys.stderr,hex(self.ARMget_register(1)) self.ARMset_register(1, r1); # restore R0 and R1 self.ARMset_register(0, r0); + def writeMemByte(self, adr, byte): + self.ARMwriteMem(adr, byte, ARM_WRITE_MEM_BYTE) + ARMstatusbits={ 0x10 : "TBIT", @@ -515,22 +578,24 @@ class GoodFETARM(GoodFET): 0x02 : "force dbgrq", 0x01 : "force dbgack" } - + def ARMresettarget(self, delay=10): + return self.writecmd(0x13,RESETTARGET,2, [ delay&0xff, (delay>>8)&0xff ] ) def ARMchain0(self, address, bits=0x819684c054, data=0): bulk = chop(address,4) bulk.extend(chop(bits,8)) bulk.extend(chop(data,4)) - print (repr(bulk)) + print >>sys.stderr,(repr(bulk)) self.writecmd(0x13,CHAIN0,16,bulk) d1,b1,a1 = struct.unpack(">sys.stderr,"Identifying Target:" ident=self.ARMidentstr() - print "Target identifies as %s." % ident - print "Debug Status: %s." % self.statusstr() - #print "System State: %x." % self.ARMget_regCPSRstr() + print >>sys.stderr,ident + print >>sys.stderr,"Debug Status:\t%s\n" % self.statusstr() + def stop(self): """Stop debugging.""" self.writecmd(0x13,STOP,0,self.data)