X-Git-Url: http://git.rot13.org/?p=goodfet;a=blobdiff_plain;f=client%2FGoodFETARM7.py;h=f7f0b94de919f432deb1958058657100f2996888;hp=be1c9539db40021379214c5167dda02e8231eb35;hb=0f09afa49bb8b723a270edd816acbdcaddeb7290;hpb=6ec4512553ac11e9893437fd80ab21992f0ab4f5 diff --git a/client/GoodFETARM7.py b/client/GoodFETARM7.py index be1c953..f7f0b94 100644 --- a/client/GoodFETARM7.py +++ b/client/GoodFETARM7.py @@ -1,8 +1,6 @@ #!/usr/bin/env python # GoodFET ARM Client Library # -# -# Good luck with alpha / beta code. # Contributions and bug reports welcome. # # todo: @@ -10,15 +8,8 @@ # * ensure correct PC handling # * flash manipulation (probably need to get the specific chip for this one) # * set security (chip-specific) -# * -ancilary/faster- ldm/stm versions of memory access (had trouble in past, possibly also due to haphazard abuse of DCLK) -# -# fixme now stuff: -# * thumb mode get/set_register -# * thumb to arm mode -# * rethink the whole python/c trade-off for cross-python session debugging import sys, binascii, struct, time -import atlasutils.smartprint as asp from GoodFET import GoodFET from intelhex import IntelHex @@ -40,10 +31,11 @@ OK = 0x7F IR_SHIFT = 0x80 DR_SHIFT = 0x81 RESETTAP = 0x82 -RESETTARGET = 0x86 -GET_REGISTER = 0x87 -SET_REGISTER = 0x88 -DEBUG_INSTR = 0x89 +RESETTARGET = 0x83 +DR_SHIFT_MORE = 0x87 +GET_REGISTER = 0x8d +SET_REGISTER = 0x8e +DEBUG_INSTR = 0x8f # Really ARM specific stuff WAIT_DBG = 0x91 CHAIN0 = 0x93 @@ -131,9 +123,12 @@ ARM_INSTR_LDR_R1_r0_4 = 0xe4901004L ARM_READ_MEM = ARM_INSTR_LDR_R1_r0_4 ARM_INSTR_STR_R1_r0_4 = 0xe4801004L ARM_WRITE_MEM = ARM_INSTR_STR_R1_r0_4 +ARM_INSTR_STRB_R1_r0_1 = 0xe4c01001L +ARM_WRITE_MEM_BYTE = ARM_INSTR_STRB_R1_r0_1 ARM_INSTR_MRS_R0_CPSR = 0xe10f0000L ARM_INSTR_MSR_cpsr_cxsf_R0 =0xe12ff000L -ARM_INSTR_STMIA_R14_r0_rx = 0xE88E0000L # add up to 65k to indicate which registers... +ARM_INSTR_STMIA_R14_r0_rx = 0xE88e0000L # add up to 65k to indicate which registers... +ARM_INSTR_LDMIA_R14_r0_rx = 0xE89e0000L # add up to 65k to indicate which registers... ARM_STORE_MULTIPLE = ARM_INSTR_STMIA_R14_r0_rx ARM_INSTR_SKANKREGS = 0xE88F7fffL ARM_INSTR_CLOBBEREGS = 0xE89F7fffL @@ -183,6 +178,12 @@ DBGCTRLBITS = { 1<>sys.stderr,(strng) @@ -216,19 +217,38 @@ class GoodFETARM(GoodFET): """Move the FET into the JTAG ARM application.""" #print "Initializing ARM." self.writecmd(0x13,SETUP,0,self.data) - def getpc(self): - return self.ARMgetPC() def flash(self,file): """Flash an intel hex file to code memory.""" print "Flash not implemented."; - def dump(self,file,start=0,stop=0xffff): + def dump(self,fn,start=0,stop=0xffffffff): """Dump an intel hex file from code memory.""" + + print "Dumping from %04x to %04x as %s." % (start,stop,f); + # FIXME: get mcu state and return it to that state + self.halt() + + h = IntelHex(None); + i=start; + while i<=stop: + data=self.ARMreadChunk(i, 48, verbose=0); + print "Dumped %06x."%i; + for dword in data: + if i<=stop and dword != 0xdeadbeef: + h.puts( i, struct.pack(">8)&0xff,(data>>16)&0xff,(data>>24)&0xff]) + self.writecmd(0x13,DR_SHIFT,14,[bits&0xff, flags&0xff, 0, 0, data&0xff,(data>>8)&0xff,(data>>16)&0xff,(data>>24)&0xff, (data>>32)&0xff,(data>>40)&0xff,(data>>48)&0xff,(data>>56)&0xff,(data>>64)&0xff,(data>>72)&0xff]) + return self.data + def ARMshift_DR_more(self, data, bits, flags): + self.writecmd(0x13,DR_SHIFT_MORE,14,[bits&0xff, flags&0xff, 0, 0, data&0xff,(data>>8)&0xff,(data>>16)&0xff,(data>>24)&0xff, (data>>32)&0xff,(data>>40)&0xff,(data>>48)&0xff,(data>>56)&0xff,(data>>64)&0xff,(data>>72)&0xff]) return self.data def ARMwaitDBG(self, timeout=0xff): self.current_dbgstate = self.ARMget_dbgstate() @@ -244,10 +264,10 @@ class GoodFETARM(GoodFET): return retval def ARMidentstr(self): ident=self.ARMident() - ver = ident >> 28 - partno = (ident >> 12) & 0x10 - mfgid = ident & 0xfff - return "mfg: %x\npartno: %x\nver: %x\n(%x)" % (ver, partno, mfgid, ident); + ver = (ident >> 28) + partno = (ident >> 12) & 0xffff + mfgid = (ident >> 1) & 0x7ff + return "Chip IDCODE: 0x%x\n\tver: %x\n\tpartno: %x\n\tmfgid: %x\n" % (ident, ver, partno, mfgid); def ARMeice_write(self, reg, val): data = chop(val,4) data.extend([reg]) @@ -284,12 +304,13 @@ class GoodFETARM(GoodFET): def ARMgetPC(self): """Get an ARM's PC. Note: real PC gets all wonky in debug mode, this is the "saved" PC""" return self.storedPC + getpc = ARMgetPC def ARMsetPC(self, val): """Set an ARM's PC. Note: real PC gets all wonky in debug mode, this changes the "saved" PC which is used when exiting debug mode""" self.storedPC = val def ARMget_register(self, reg): """Get an ARM's Register""" - self.writecmd(0x13,GET_REGISTER,1,[reg&0xff]) + self.writecmd(0x13,GET_REGISTER,1,[reg&0xf]) retval = struct.unpack("0: + out.append( struct.pack(" 0): + if (verbose and wordcount%64 == 0): sys.stderr.write(".") + count = (wordcount, 0xe)[wordcount>0xd] + bitmask = LDM_BITMASKS[count] + self.ARMset_register(14,adr) + self.ARM_nop(1) + self.ARMdebuginstr(ARM_INSTR_LDMIA_R14_r0_rx | bitmask ,0) + #FIXME: do we need the extra nop here? + self.ARMrestart() + self.ARMwaitDBG() + for x in range(count): + yield self.ARMget_register(x) + wordcount -= count + adr += count*4 + #print hex(adr) + # FIXME: handle the rest of the wordcount here. + self.ARMset_registers(regs,0xe) + #return output + + ARMreadMem = ARMreadChunk + peek = ARMreadMem + '''def ARMreadStream(self, adr, bytecount): + data = [struct.unpack(" 0): + if (wordcount%64 == 0): sys.stderr.write(".") + count = (wordcount, 0xe)[wordcount>0xd] + bitmask = LDM_BITMASKS[count] + self.ARMset_register(14,adr) + #print len(wordarray),bin(bitmask) + self.ARMset_registers(wordarray[:count],bitmask) + self.ARM_nop(1) + self.ARMdebuginstr(ARM_INSTR_STMIA_R14_r0_rx | bitmask ,0) + #FIXME: do we need the extra nop here? + self.ARMrestart() + self.ARMwaitDBG() + wordarray = wordarray[count:] + wordcount -= count + adr += count*4 + #print hex(adr) + # FIXME: handle the rest of the wordcount here. + ''' + def ARMwriteMem(self, adr, wordarray, instr=ARM_WRITE_MEM): r0 = self.ARMget_register(0); # store R0 and R1 r1 = self.ARMget_register(1); #print >>sys.stderr,("CPSR:\t%x"%self.ARMget_regCPSR()) @@ -495,13 +622,55 @@ class GoodFETARM(GoodFET): self.ARMset_register(1, word); # write address into R0 self.ARM_nop(0) self.ARM_nop(1) - self.ARMdebuginstr(ARM_WRITE_MEM, 0); # push STR R1, [R0], #4 into instruction pipeline (autoincrements for consecutive writes) + self.ARMdebuginstr(instr, 0); # push STR R1, [R0], #4 into instruction pipeline (autoincrements for consecutive writes) self.ARM_nop(0) self.ARMrestart() self.ARMwaitDBG() - print hex(self.ARMget_register(1)) + #print >>sys.stderr,hex(self.ARMget_register(1)) self.ARMset_register(1, r1); # restore R0 and R1 self.ARMset_register(0, r0); + ''' + ARMwriteMem = ARMwriteChunk + + def ARMwriteStream(self, addr, datastr): + #bytecount = len(datastr) + #baseaddr = addr & 0xfffffffc + #diffstart = addr - baseaddr + #endaddr = ((addr + bytecount) & 0xfffffffc) + 4 + #diffend = 4 - (endaddr - (addr+bytecount)) + bytecount = len(datastr) + baseaddr = addr & 0xfffffffc + endaddr = ((addr + bytecount + 3) & 0xfffffffc) + diffstart = 4 - (addr - baseaddr) + diffend = 4 - (endaddr - (addr + bytecount )) + + print hex(baseaddr), hex(diffstart), hex(endaddr), hex(diffend) + out = [] + if diffstart: + dword = self.ARMreadChunk(baseaddr, 1)[0] & (0xffffffff>>(8*diffstart)) + dst = "\x00" * (4-diffstart) + datastr[:diffstart]; print hex(dword), repr(dst) + datachk = struct.unpack(">8)&0xff ] ) + def ARMchain0(self, address, bits=0x819684c054, data=0): bulk = chop(address,4) bulk.extend(chop(bits,8)) bulk.extend(chop(data,4)) - print (repr(bulk)) + #print >>sys.stderr,(repr(bulk)) self.writecmd(0x13,CHAIN0,16,bulk) d1,b1,a1 = struct.unpack(">sys.stderr,"Identifying Target:" ident=self.ARMidentstr() - print "Target identifies as %s." % ident - print "Debug Status: %s." % self.statusstr() - #print "System State: %x." % self.ARMget_regCPSRstr() + print >>sys.stderr,ident + print >>sys.stderr,"Debug Status:\t%s\n" % self.statusstr() + def stop(self): """Stop debugging.""" self.writecmd(0x13,STOP,0,self.data)