X-Git-Url: http://git.rot13.org/?p=goodfet;a=blobdiff_plain;f=firmware%2Fapps%2Fchipcon%2Fchipcon.c;h=7ce22b2479ddd3ed915892e1bcd3d6f74785a994;hp=83bc898a39b7ad4b7fc39f56b558122427e6acaf;hb=da936efd54c94f9d801ef07bdd08f533dac5b641;hpb=363ca47c79cf3a39dca93a54fe48e0253c946c8b

diff --git a/firmware/apps/chipcon/chipcon.c b/firmware/apps/chipcon/chipcon.c
index 83bc898..7ce22b2 100644
--- a/firmware/apps/chipcon/chipcon.c
+++ b/firmware/apps/chipcon/chipcon.c
@@ -59,6 +59,7 @@ app_t const chipcon_app = {
 //This could be more accurate.
 //Does it ever need to be?
 #define CCSPEED 3
+//#define CCSPEED 3
 //#define CCDELAY(x) delay(x)
 #define CCDELAY(x) 
 
@@ -99,7 +100,7 @@ void ccdebuginit(){
   //Port output BUT NOT DIRECTION is set at start.
   SPIOUT|=MOSI+SCK+RST;
   
-  //delay(30); //So the beginning is ready for glitching.
+  delay(30); //So the beginning is ready for glitching.
   
   //Two positive debug clock pulses while !RST is low.
   //Take RST low, pulse twice, then high.
@@ -139,11 +140,11 @@ unsigned char cctrans8(unsigned char byte){
     byte <<= 1;
  
     /* half a clock cycle before leading/rising edge */
-    CCDELAY(CCSPEED/2);
+    CCDELAY(CCSPEED>>2);
     SETCLK;
  
     /* half a clock cycle before trailing/falling edge */
-    CCDELAY(CCSPEED/2);
+    CCDELAY(CCSPEED>>2);
  
     /* read MISO on trailing edge */
     byte |= READMISO;
@@ -262,7 +263,7 @@ void cc_handle_fn( uint8_t const app,
     txdata(app,verb,1);
     break;
   case CC_STEP_REPLACE:
-    txdata(app,NOK,0);//TODO add me
+    txdata(app,NOK,0);//Don't add this; it's non-standard.
     break;
   case CC_GET_CHIP_ID:
     cmddataword[0]=cc_get_chip_id();