X-Git-Url: http://git.rot13.org/?p=goodfet;a=blobdiff_plain;f=firmware%2Fapps%2Fjtag%2Fjtag430.c;h=52cfa71f887ae2de0ea1330a529d716986dd4f23;hp=9260b0cc2832a520d6a95be107e24ac2668e8e7e;hb=0351243d52f70e34790269e600c65413ddb4bc7c;hpb=1706a7f4cfa73ed716b56f5b0322bfb67b560ade diff --git a/firmware/apps/jtag/jtag430.c b/firmware/apps/jtag/jtag430.c index 9260b0c..52cfa71 100644 --- a/firmware/apps/jtag/jtag430.c +++ b/firmware/apps/jtag/jtag430.c @@ -10,23 +10,31 @@ unsigned int jtag430mode=MSP430X2MODE; -//! Set the program counter. -void jtag430_setpc(unsigned int adr){ +//! Set a register. +void jtag430_setr(u8 reg, u16 val){ jtag_ir_shift8(IR_CNTRL_SIG_16BIT); jtag_dr_shift16(0x3401);// release low byte jtag_ir_shift8(IR_DATA_16BIT); - jtag_dr_shift16(0x4030);//Instruction to load PC + + //0x4030 is "MOV #foo, r0" + //Right-most field is register, so 0x4035 loads r5 + jtag_dr_shift16(0x4030+reg); CLRTCLK; SETTCLK; - jtag_dr_shift16(adr);// Value for PC + jtag_dr_shift16(val);// Value for the register CLRTCLK; jtag_ir_shift8(IR_ADDR_CAPTURE); SETTCLK; - CLRTCLK ;// Now PC is set to "PC_Value" + CLRTCLK ;// Now reg is set to new value. jtag_ir_shift8(IR_CNTRL_SIG_16BIT); jtag_dr_shift16(0x2401);// low byte controlled by JTAG } +//! Set the program counter. +void jtag430_setpc(unsigned int adr){ + jtag430_setr(0,adr); +} + //! Halt the CPU void jtag430_haltcpu(){ //jtag430_setinstrfetch(); @@ -43,15 +51,21 @@ void jtag430_haltcpu(){ //! Release the CPU void jtag430_releasecpu(){ CLRTCLK; + //debugstr("Releasing target MSP430."); + + /* jtag_ir_shift8(IR_CNTRL_SIG_16BIT); - jtag_dr_shift16(0x2401); - jtag_ir_shift8(IR_ADDR_CAPTURE); + jtag_dr_shift16(0x2C01); //Apply reset. + jtag_dr_shift16(0x2401); //Release reset. + */ + jtag_ir_shift8(IR_CNTRL_SIG_RELEASE); SETTCLK; } //! Read data from address unsigned int jtag430_readmem(unsigned int adr){ unsigned int toret; + jtag430_haltcpu(); CLRTCLK; jtag_ir_shift8(IR_CNTRL_SIG_16BIT); @@ -61,7 +75,7 @@ unsigned int jtag430_readmem(unsigned int adr){ else jtag_dr_shift16(0x2419);//byte read jtag_ir_shift8(IR_ADDR_16BIT); - jtag_dr_shift16(adr);//address + jtag_dr_shiftadr(adr);//address jtag_ir_shift8(IR_DATA_TO_ADDR); SETTCLK; @@ -80,7 +94,7 @@ void jtag430_writemem(unsigned int adr, unsigned int data){ else jtag_dr_shift16(0x2418);//byte write jtag_ir_shift8(IR_ADDR_16BIT); - jtag_dr_shift16(adr); + jtag_dr_shiftadr(adr); jtag_ir_shift8(IR_DATA_TO_ADDR); jtag_dr_shift16(data); SETTCLK; @@ -88,12 +102,12 @@ void jtag430_writemem(unsigned int adr, unsigned int data){ //! Write data to flash memory. Must be preconfigured. void jtag430_writeflashword(unsigned int adr, unsigned int data){ - /* + CLRTCLK; jtag_ir_shift8(IR_CNTRL_SIG_16BIT); jtag_dr_shift16(0x2408);//word write jtag_ir_shift8(IR_ADDR_16BIT); - jtag_dr_shift16(adr); + jtag_dr_shiftadr(adr); jtag_ir_shift8(IR_DATA_TO_ADDR); jtag_dr_shift16(data); SETTCLK; @@ -102,16 +116,16 @@ void jtag430_writeflashword(unsigned int adr, unsigned int data){ CLRTCLK; jtag_ir_shift8(IR_CNTRL_SIG_16BIT); jtag_dr_shift16(0x2409); - */ + /* jtag430_writemem(adr,data); CLRTCLK; jtag_ir_shift8(IR_CNTRL_SIG_16BIT); jtag_dr_shift16(0x2409); + */ //Pulse TCLK jtag430_tclk_flashpulses(35); //35 standard - } //! Configure flash, then write a word. @@ -123,7 +137,8 @@ void jtag430_writeflash(unsigned int adr, unsigned int data){ //FCTL2=0xA540, selecting MCLK as source, DIV=1 jtag430_writemem(0x012A, 0xA540); //FCTL3=0xA500, should be 0xA540 for Info Seg A on 2xx chips. - jtag430_writemem(0x012C, 0xA500); + jtag430_writemem(0x012C, 0xA500); //all but info flash. + //if(jtag430_readmem(0x012C)); //Write the word itself. jtag430_writeflashword(adr,data); @@ -131,7 +146,7 @@ void jtag430_writeflash(unsigned int adr, unsigned int data){ //FCTL1=0xA500, disabling flash write jtag430_writemem(0x0128, 0xA500); - jtag430_releasecpu(); + //jtag430_releasecpu(); } @@ -164,7 +179,8 @@ void jtag430_por(){ #define ERASE_SGMT 0xA502 //! Configure flash, then write a word. -void jtag430_eraseflash(unsigned int mode, unsigned int adr, unsigned int count){ +void jtag430_eraseflash(unsigned int mode, unsigned int adr, unsigned int count, + unsigned int info){ jtag430_haltcpu(); //FCTL1= erase mode @@ -172,7 +188,10 @@ void jtag430_eraseflash(unsigned int mode, unsigned int adr, unsigned int count) //FCTL2=0xA540, selecting MCLK as source, DIV=1 jtag430_writemem(0x012A, 0xA540); //FCTL3=0xA500, should be 0xA540 for Info Seg A on 2xx chips. - jtag430_writemem(0x012C, 0xA500); + if(info) + jtag430_writemem(0x012C, 0xA540); + else + jtag430_writemem(0x012C, 0xA500); //Write the erase word. jtag430_writemem(adr, 0x55AA); @@ -187,7 +206,7 @@ void jtag430_eraseflash(unsigned int mode, unsigned int adr, unsigned int count) //FCTL1=0xA500, disabling flash write jtag430_writemem(0x0128, 0xA500); - jtag430_releasecpu(); + //jtag430_releasecpu(); } @@ -198,19 +217,17 @@ void jtag430_resettap(){ SETTDI; //430X2 SETTMS; //SETTDI; //classic - SETTCK; + TCKTOCK; // Navigate to reset state. // Should be at least six. for(i=0;i<4;i++){ - CLRTCK; - SETTCK; + TCKTOCK; } // test-logic-reset - CLRTCK; CLRTMS; - SETTCK; + TCKTOCK; SETTMS; // idle @@ -237,7 +254,9 @@ void jtag430_start(){ SETTST; SETRST; delay(0xFFFF); - + + + #ifndef SBWREWRITE //Entry sequence from Page 67 of SLAU265A for 4-wire MSP430 JTAG CLRRST; delay(100); //100 @@ -248,13 +267,39 @@ void jtag430_start(){ SETRST; P5DIR&=~RST; delay(0xFFFF); + #endif //Perform a reset and disable watchdog. jtag430_por(); + jtag430_writemem(0x120,0x5a80);//disable watchdog + + jtag430_haltcpu(); +} + +//! Stop JTAG. +void jtag430_stop(){ + debugstr("Exiting JTAG."); + jtagsetup(); + + //Known-good starting position. + //Might be unnecessary. + //SETTST; + CLRTST; + SETRST; + delay(0xFFFF); + + //Entry sequence from Page 67 of SLAU265A for 4-wire MSP430 JTAG + CLRRST; + delay(0xFFFF); + SETRST; + //P5DIR&=~RST; + //delay(0xFFFF); + } //! Set CPU to Instruction Fetch void jtag430_setinstrfetch(){ + jtag_ir_shift8(IR_CNTRL_SIG_CAPTURE); // Wait until instruction fetch state. @@ -268,13 +313,29 @@ void jtag430_setinstrfetch(){ //! Handles classic MSP430 JTAG commands. Forwards others to JTAG. -void oldjtag430handle(unsigned char app, +void jtag430handle(unsigned char app, unsigned char verb, - unsigned char len){ - register char blocks; + unsigned long len){ unsigned long at; unsigned int i, val; + //debugstr("Classic MSP430 handler."); + + + /* FIXME + * Sometimes JTAG doesn't init correctly. + * This restarts the connection if the masked-rom + * chip ID cannot be read. Should print warning + * for testing server. + */ + while((i=jtag430_readmem(0xff0))==0xFFFF){ + debugstr("Reconnecting to target MSP430."); + jtag430_start(); + PLEDOUT^=PLEDPIN; + } + PLEDOUT&=~PLEDPIN; + + switch(verb){ case START: //Enter JTAG mode. @@ -282,6 +343,12 @@ void oldjtag430handle(unsigned char app, //TAP setup, fuse check jtag430_resettap(); + cmddata[0]=jtag_ir_shift8(IR_BYPASS); + txdata(app,verb,1); + + break; + case STOP: + jtag430_stop(); txdata(app,verb,0); break; case JTAG430_HALTCPU: @@ -299,56 +366,90 @@ void oldjtag430handle(unsigned char app, case JTAG430_READMEM: case PEEK: - /* - cmddataword[0]=jtag430_readmem(cmddataword[0]); - txdata(app,verb,2); - */ - blocks=(len>4?cmddata[4]:1); at=cmddatalong[0]; - len=0x80; - serial_tx(app); - serial_tx(verb); - serial_tx(len); + //Fetch large blocks for bulk fetches, + //small blocks for individual peeks. + if(len>5) + len=(cmddataword[2]);//always even. + else + len=2; + len&=~1;//clear lsbit - while(blocks--){ - for(i=0;i>8); - } + txhead(app,verb,len); + for(i=0;i>8); } - - - break; case JTAG430_WRITEMEM: case POKE: - jtag430_writemem(cmddatalong[0],cmddataword[2]); - cmddataword[0]=jtag430_readmem(cmddatalong[0]); + jtag430_haltcpu(); + jtag430_writemem(cmddataword[0],cmddataword[2]); + cmddataword[0]=jtag430_readmem(cmddataword[0]); txdata(app,verb,2); break; + /* + case JTAG430_WRITEFLASH: + + //debugstr("Poking flash memory."); + jtag430_writeflash(cmddataword[0],cmddataword[2]); + + //Try again if failure. + //if(cmddataword[2]!=jtag430_readmem(cmddataword[0])) + // jtag430_writeflash(cmddataword[0],cmddataword[2]); + + //Return result. + cmddataword[0]=jtag430_readmem(cmddataword[0]); + + txdata(app,verb,2); + break; */ case JTAG430_WRITEFLASH: - jtag430_writeflash(cmddataword[0],cmddataword[1]); + at=cmddataword[0]; + + for(i=0;i<(len>>1)-2;i++){ + //debugstr("Poking flash memory."); + jtag430_writeflash(at+(i<<1),cmddataword[i+2]); + //Reflash if needed. Try this twice to save grace? + if(cmddataword[i]!=jtag430_readmem(at)) + jtag430_writeflash(at+(i<<1),cmddataword[i+2]); + } + + //Return result of first write as a word. cmddataword[0]=jtag430_readmem(cmddataword[0]); + txdata(app,verb,2); break; case JTAG430_ERASEFLASH: - jtag430_eraseflash(ERASE_MASS,0xFFFE,0xFFFF); - jtag430_eraseflash(ERASE_MASS,0xFFFE,0xFFFF); - jtag430_eraseflash(ERASE_MASS,0xFFFE,0xFFFF); + jtag430_eraseflash(ERASE_MASS,0xFFFE,0x3000,0); + txdata(app,verb,0); + break; + case JTAG430_ERASEINFO: + jtag430_eraseflash(ERASE_SGMT,0x1000,0x3000,1); txdata(app,verb,0); break; case JTAG430_SETPC: + jtag430_haltcpu(); + //debughex("Setting PC."); + //debughex(cmddataword[0]); jtag430_setpc(cmddataword[0]); + jtag430_releasecpu(); txdata(app,verb,0); break; - + case JTAG430_SETREG: + jtag430_setr(cmddata[0],cmddataword[1]); + txdata(app,verb,0); + break; + case JTAG430_GETREG: + //jtag430_getr(cmddata[0]); + debugstr("JTAG430_GETREG not yet implemented."); + cmddataword[0]=0xDEAD; + txdata(app,verb,2); + break; case JTAG430_COREIP_ID: case JTAG430_DEVICE_ID: cmddataword[0]=0; @@ -359,19 +460,5 @@ void oldjtag430handle(unsigned char app, default: jtaghandle(app,verb,len); } - jtag430_resettap(); -} - -//! Handles unique MSP430 JTAG commands. Forwards others to JTAG. -void jtag430handle(unsigned char app, - unsigned char verb, - unsigned char len){ - switch(jtag430mode){ - case MSP430MODE: - return oldjtag430handle(app,verb,len); - case MSP430X2MODE: - return jtag430x2handle(app,verb,len); - default: - txdata(app,NOK,0); - } + //jtag430_resettap(); //DO NOT UNCOMMENT }