X-Git-Url: http://git.rot13.org/?p=goodfet;a=blobdiff_plain;f=firmware%2Fapps%2Fjtag%2Fjtag430.c;h=52cfa71f887ae2de0ea1330a529d716986dd4f23;hp=d704e86e615a306157aab8eb08dcb62ea76ef8e5;hb=c1ef7ebcf885f8eac4fb047a376393fc7c7de196;hpb=5c029aa0c4f7573d9fa49beefe6e887dee2b25f9

diff --git a/firmware/apps/jtag/jtag430.c b/firmware/apps/jtag/jtag430.c
index d704e86..52cfa71 100644
--- a/firmware/apps/jtag/jtag430.c
+++ b/firmware/apps/jtag/jtag430.c
@@ -51,9 +51,14 @@ void jtag430_haltcpu(){
 //! Release the CPU
 void jtag430_releasecpu(){
   CLRTCLK;
+  //debugstr("Releasing target MSP430.");
+  
+  /*
   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
-  jtag_dr_shift16(0x2401);
-  jtag_ir_shift8(IR_ADDR_CAPTURE);
+  jtag_dr_shift16(0x2C01); //Apply reset.
+  jtag_dr_shift16(0x2401); //Release reset.
+  */
+  jtag_ir_shift8(IR_CNTRL_SIG_RELEASE);
   SETTCLK;
 }
 
@@ -133,6 +138,7 @@ void jtag430_writeflash(unsigned int adr, unsigned int data){
   jtag430_writemem(0x012A, 0xA540);
   //FCTL3=0xA500, should be 0xA540 for Info Seg A on 2xx chips.
   jtag430_writemem(0x012C, 0xA500); //all but info flash.
+  //if(jtag430_readmem(0x012C));
   
   //Write the word itself.
   jtag430_writeflashword(adr,data);
@@ -323,10 +329,11 @@ void jtag430handle(unsigned char app,
    * for testing server.
    */
   while((i=jtag430_readmem(0xff0))==0xFFFF){
+    debugstr("Reconnecting to target MSP430.");
     jtag430_start();
-    P1OUT^=1;
+    PLEDOUT^=PLEDPIN;
   }
-  P1OUT&=~1;
+  PLEDOUT&=~PLEDPIN;
   
   
   switch(verb){
@@ -422,12 +429,15 @@ void jtag430handle(unsigned char app,
     txdata(app,verb,0);
     break;
   case JTAG430_ERASEINFO:
-    jtag430_eraseflash(ERASE_MASS,0xFFFE,0x3000,1);
+    jtag430_eraseflash(ERASE_SGMT,0x1000,0x3000,1);
     txdata(app,verb,0);
     break;
   case JTAG430_SETPC:
     jtag430_haltcpu();
+    //debughex("Setting PC.");
+    //debughex(cmddataword[0]);
     jtag430_setpc(cmddataword[0]);
+    jtag430_releasecpu();
     txdata(app,verb,0);
     break;
   case JTAG430_SETREG: