X-Git-Url: http://git.rot13.org/?p=goodfet;a=blobdiff_plain;f=firmware%2Fapps%2Fjtag%2Fjtag430.c;h=65d4e3183780a59b186bb1b33f666dd4596f475d;hp=081fb52427368ba49aa95e39d7d24850c8bb5dca;hb=32f20cd81c67f9cfb9bd11b9b62942ff60d9b2f4;hpb=7487b2cd89324081ccfc195d49f4158f10ec534f

diff --git a/firmware/apps/jtag/jtag430.c b/firmware/apps/jtag/jtag430.c
index 081fb52..65d4e31 100644
--- a/firmware/apps/jtag/jtag430.c
+++ b/firmware/apps/jtag/jtag430.c
@@ -4,6 +4,8 @@
 #include "jtag.h"
 
 
+unsigned int jtag430mode=MSP430X2MODE;
+
 //! Set the program counter.
 void jtag430_setpc(unsigned int adr){
   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
@@ -49,6 +51,7 @@ unsigned int jtag430_readmem(unsigned int adr){
   
   CLRTCLK;
   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
+  
   if(adr>0xFF)
     jtag_dr_shift16(0x2409);//word read
   else
@@ -79,28 +82,6 @@ void jtag430_writemem(unsigned int adr, unsigned int data){
   SETTCLK;
 }
 
-//! Defined in jtag430asm.S
-void jtag430_tclk_flashpulses(int);
-/* //! Pulse TCLK at 350kHz +/- 100kHz */
-/* void jtag430_tclk_flashpulses(register i){ */
-/*   //TODO check this on a scope. */
-/*   register j=0; */
-  
-/*   //At 2MHz, 350kHz is obtained with 5 clocks of delay */
-  
-/*   /\** Pondering: */
-/*       What happens if the frequency is too low or to high? */
-/*       Is there any risk of damaging the chip, or only of a poor write? */
-/*   *\/ */
-/*   while(j++!=i){ */
-/*     SETTCLK; */
-/*     _NOP(); */
-/*     _NOP(); */
-/*     _NOP(); */
-/*     CLRTCLK; */
-/*   } */
-/* } */
-
 //! Write data to flash memory.  Must be preconfigured.
 void jtag430_writeflashword(unsigned int adr, unsigned int data){
   /*
@@ -151,6 +132,27 @@ void jtag430_writeflash(unsigned int adr, unsigned int data){
 
 
 
+//! Power-On Reset
+void jtag430_por(){
+  unsigned int jtagid;
+
+  // Perform Reset
+  jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
+  jtag_dr_shift16(0x2C01); // apply
+  jtag_dr_shift16(0x2401); // remove
+  CLRTCLK;
+  SETTCLK;
+  CLRTCLK;
+  SETTCLK;
+  CLRTCLK;
+  jtagid = jtag_ir_shift8(IR_ADDR_CAPTURE); // get JTAG identifier
+  SETTCLK;
+  
+  jtag430_writemem(0x0120, 0x5A80);   // Diabled Watchdog
+}
+
+
+
 #define ERASE_GLOB 0xA50E
 #define ERASE_ALLMAIN 0xA50C
 #define ERASE_MASS 0xA506
@@ -159,6 +161,8 @@ void jtag430_writeflash(unsigned int adr, unsigned int data){
 
 //! Configure flash, then write a word.
 void jtag430_eraseflash(unsigned int mode, unsigned int adr, unsigned int count){
+  jtag430_haltcpu();
+  
   //FCTL1= erase mode
   jtag430_writemem(0x0128, mode);
   //FCTL2=0xA540, selecting MCLK as source, DIV=1
@@ -178,6 +182,8 @@ void jtag430_eraseflash(unsigned int mode, unsigned int adr, unsigned int count)
   
   //FCTL1=0xA500, disabling flash write
   jtag430_writemem(0x0128, 0xA500);
+  
+  jtag430_releasecpu();
 }
 
 
@@ -237,6 +243,9 @@ void jtag430_start(){
   SETRST;
   P5DIR&=~RST;
   delay(0xFFFF);
+  
+  //Perform a reset and disable watchdog.
+  jtag430_por();
 }
 
 //! Set CPU to Instruction Fetch
@@ -252,11 +261,12 @@ void jtag430_setinstrfetch(){
   }
 }
 
-//! Handles unique MSP430 JTAG commands.  Forwards others to JTAG.
-void jtag430handle(unsigned char app,
+
+//! Handles classic MSP430 JTAG commands.  Forwards others to JTAG.
+void oldjtag430handle(unsigned char app,
 		   unsigned char verb,
 		   unsigned char len){
-  unsigned char i;
+  
   switch(verb){
   case START:
     //Enter JTAG mode.
@@ -311,3 +321,16 @@ void jtag430handle(unsigned char app,
   jtag430_resettap();
 }
 
+//! Handles unique MSP430 JTAG commands.  Forwards others to JTAG.
+void jtag430handle(unsigned char app,
+		   unsigned char verb,
+		   unsigned char len){
+  switch(jtag430mode){
+  case MSP430MODE:
+    return oldjtag430handle(app,verb,len);
+  case MSP430X2MODE:
+    return jtag430x2handle(app,verb,len);
+  default:
+    txdata(app,NOK,0);
+  }
+}