X-Git-Url: http://git.rot13.org/?p=goodfet;a=blobdiff_plain;f=firmware%2Fapps%2Fjtag%2Fjtag430.c;h=a8a07bd49d09373dd4a387073af6b2c9183ced4d;hp=0d1fbfb7791e38bfd9d688b17ab4ea80d441df3e;hb=c1105ada99267eaceb19d45d422b7d652e619b2e;hpb=6dc88d2f1713d2bf9f2fabb5fbfb9f235a679b2f diff --git a/firmware/apps/jtag/jtag430.c b/firmware/apps/jtag/jtag430.c index 0d1fbfb..a8a07bd 100644 --- a/firmware/apps/jtag/jtag430.c +++ b/firmware/apps/jtag/jtag430.c @@ -5,28 +5,57 @@ #include "platform.h" #include "command.h" -#include "jtag.h" +#include "jtag430.h" +//! Handles classic MSP430 JTAG commands. Forwards others to JTAG. +void jtag430_handle_fn(uint8_t const app, + uint8_t const verb, + uint32_t const len); + +// define the jtag430 app's app_t +app_t const jtag430_app = { + + /* app number */ + JTAG430, + + /* handle fn */ + jtag430_handle_fn, + + /* name */ + "JTAG430", + + /* desc */ + "\tThe JTAG430 app adds to the basic JTAG app\n" + "\tsupport for JTAG'ing MSP430 devices.\n" +}; unsigned int jtag430mode=MSP430X2MODE; -//! Set the program counter. -void jtag430_setpc(unsigned int adr){ +//! Set a register. +void jtag430_setr(u8 reg, u16 val){ jtag_ir_shift8(IR_CNTRL_SIG_16BIT); jtag_dr_shift16(0x3401);// release low byte jtag_ir_shift8(IR_DATA_16BIT); - jtag_dr_shift16(0x4030);//Instruction to load PC + + //0x4030 is "MOV #foo, r0" + //Right-most field is register, so 0x4035 loads r5 + jtag_dr_shift16(0x4030+reg); CLRTCLK; SETTCLK; - jtag_dr_shift16(adr);// Value for PC + jtag_dr_shift16(val);// Value for the register CLRTCLK; jtag_ir_shift8(IR_ADDR_CAPTURE); SETTCLK; - CLRTCLK ;// Now PC is set to "PC_Value" + CLRTCLK ;// Now reg is set to new value. jtag_ir_shift8(IR_CNTRL_SIG_16BIT); jtag_dr_shift16(0x2401);// low byte controlled by JTAG } +//! Set the program counter. +void jtag430_setpc(unsigned int adr){ + jtag430_setr(0,adr); +} + //! Halt the CPU void jtag430_haltcpu(){ //jtag430_setinstrfetch(); @@ -43,9 +72,14 @@ void jtag430_haltcpu(){ //! Release the CPU void jtag430_releasecpu(){ CLRTCLK; + //debugstr("Releasing target MSP430."); + + /* jtag_ir_shift8(IR_CNTRL_SIG_16BIT); - jtag_dr_shift16(0x2401); - jtag_ir_shift8(IR_ADDR_CAPTURE); + jtag_dr_shift16(0x2C01); //Apply reset. + jtag_dr_shift16(0x2401); //Release reset. + */ + jtag_ir_shift8(IR_CNTRL_SIG_RELEASE); SETTCLK; } @@ -62,7 +96,7 @@ unsigned int jtag430_readmem(unsigned int adr){ else jtag_dr_shift16(0x2419);//byte read jtag_ir_shift8(IR_ADDR_16BIT); - jtag_dr_shift16(adr);//address + jtag_dr_shiftadr(adr);//address jtag_ir_shift8(IR_DATA_TO_ADDR); SETTCLK; @@ -81,7 +115,7 @@ void jtag430_writemem(unsigned int adr, unsigned int data){ else jtag_dr_shift16(0x2418);//byte write jtag_ir_shift8(IR_ADDR_16BIT); - jtag_dr_shift16(adr); + jtag_dr_shiftadr(adr); jtag_ir_shift8(IR_DATA_TO_ADDR); jtag_dr_shift16(data); SETTCLK; @@ -94,7 +128,7 @@ void jtag430_writeflashword(unsigned int adr, unsigned int data){ jtag_ir_shift8(IR_CNTRL_SIG_16BIT); jtag_dr_shift16(0x2408);//word write jtag_ir_shift8(IR_ADDR_16BIT); - jtag_dr_shift16(adr); + jtag_dr_shiftadr(adr); jtag_ir_shift8(IR_DATA_TO_ADDR); jtag_dr_shift16(data); SETTCLK; @@ -125,6 +159,7 @@ void jtag430_writeflash(unsigned int adr, unsigned int data){ jtag430_writemem(0x012A, 0xA540); //FCTL3=0xA500, should be 0xA540 for Info Seg A on 2xx chips. jtag430_writemem(0x012C, 0xA500); //all but info flash. + //if(jtag430_readmem(0x012C)); //Write the word itself. jtag430_writeflashword(adr,data); @@ -165,7 +200,8 @@ void jtag430_por(){ #define ERASE_SGMT 0xA502 //! Configure flash, then write a word. -void jtag430_eraseflash(unsigned int mode, unsigned int adr, unsigned int count){ +void jtag430_eraseflash(unsigned int mode, unsigned int adr, unsigned int count, + unsigned int info){ jtag430_haltcpu(); //FCTL1= erase mode @@ -173,7 +209,10 @@ void jtag430_eraseflash(unsigned int mode, unsigned int adr, unsigned int count) //FCTL2=0xA540, selecting MCLK as source, DIV=1 jtag430_writemem(0x012A, 0xA540); //FCTL3=0xA500, should be 0xA540 for Info Seg A on 2xx chips. - jtag430_writemem(0x012C, 0xA500); + if(info) + jtag430_writemem(0x012C, 0xA540); + else + jtag430_writemem(0x012C, 0xA500); //Write the erase word. jtag430_writemem(adr, 0x55AA); @@ -199,19 +238,17 @@ void jtag430_resettap(){ SETTDI; //430X2 SETTMS; //SETTDI; //classic - SETTCK; + TCKTOCK; // Navigate to reset state. // Should be at least six. for(i=0;i<4;i++){ - CLRTCK; - SETTCK; + TCKTOCK; } // test-logic-reset - CLRTCK; CLRTMS; - SETTCK; + TCKTOCK; SETTMS; // idle @@ -229,16 +266,59 @@ void jtag430_resettap(){ } +unsigned char jtagid; + +//! Get the JTAG ID +unsigned char jtag430x2_jtagid(){ + jtag430_resettap(); + jtagid=jtag_ir_shift8(IR_BYPASS); + if(jtagid!=0x89 && jtagid!=0x91){ + debugstr("Unknown JTAG ID"); + debughex(jtagid); + } + return jtagid; +} //! Start JTAG, take pins -void jtag430_start(){ +unsigned char jtag430x2_start(){ jtagsetup(); //Known-good starting position. //Might be unnecessary. SETTST; SETRST; + delay(0xFFFF); + //Entry sequence from Page 67 of SLAU265A for 4-wire MSP430 JTAG + CLRRST; + delay(20);//10 + CLRTST; + + delay(10);//5 + SETTST; + msdelay(10);//5 + SETRST; + P5DIR&=~RST; + + delay(0xFFFF); + + //Perform a reset and disable watchdog. + return jtag430x2_jtagid(); +} + + +//! Start JTAG, take pins +void jtag430_start(){ + jtagsetup(); + + //Known-good starting position. + //Might be unnecessary. + SETTST; + SETRST; + delay(0xFFFF); + + + #ifndef SBWREWRITE //Entry sequence from Page 67 of SLAU265A for 4-wire MSP430 JTAG CLRRST; delay(100); //100 @@ -249,6 +329,7 @@ void jtag430_start(){ SETRST; P5DIR&=~RST; delay(0xFFFF); + #endif //Perform a reset and disable watchdog. jtag430_por(); @@ -257,6 +338,27 @@ void jtag430_start(){ jtag430_haltcpu(); } +//! Stop JTAG. +void jtag430_stop(){ + debugstr("Exiting JTAG."); + jtagsetup(); + + //Known-good starting position. + //Might be unnecessary. + //SETTST; + CLRTST; + SETRST; + delay(0xFFFF); + + //Entry sequence from Page 67 of SLAU265A for 4-wire MSP430 JTAG + CLRRST; + delay(0xFFFF); + SETRST; + //P5DIR&=~RST; + //delay(0xFFFF); + +} + //! Set CPU to Instruction Fetch void jtag430_setinstrfetch(){ @@ -271,23 +373,81 @@ void jtag430_setinstrfetch(){ } } +//! Grab the core ID. +unsigned int jtag430_coreid(){ + jtag_ir_shift8(IR_COREIP_ID); + return jtag_dr_shift16(0); +} + +//! Grab the device ID. +unsigned long jtag430_deviceid(){ + jtag_ir_shift8(IR_DEVICE_ID); + return jtag_dr_shift20(0); +} + + + //! Handles classic MSP430 JTAG commands. Forwards others to JTAG. -void jtag430handle(unsigned char app, - unsigned char verb, - unsigned long len){ - unsigned long at; +void jtag430_handle_fn(uint8_t const app, + uint8_t const verb, + uint32_t const len) +{ + unsigned long at, l; unsigned int i, val; - //debugstr("Classic MSP430 handler."); + + /* FIXME + * Sometimes JTAG doesn't init correctly. + * This restarts the connection if the masked-rom + * chip ID cannot be read. Should print warning + * for testing server. + */ + while((i=jtag430_readmem(0xff0))==0xFFFF){ + debugstr("Reconnecting to target MSP430."); + jtag430x2_start(); + PLEDOUT^=PLEDPIN; + } + PLEDOUT&=~PLEDPIN; + switch(verb){ case START: + /* old method, classic MSP430. //Enter JTAG mode. - jtag430_start(); + jtag430x2_start(); //TAP setup, fuse check jtag430_resettap(); + cmddata[0]=jtag_ir_shift8(IR_BYPASS); + txdata(app,verb,1); + */ + jtag430x2_start(); + cmddata[0]=jtagid; + + jtag430mode=MSP430MODE; + + /* So the way this works is that a width of 20 does some + backward-compatibility finagling, causing the correct value + to be exchanged for addresses on 16-bit chips as well as the + new MSP430X chips. (This has only been verified on the + MSP430F2xx family. TODO verify for others.) + */ + + drwidth=20; + + //Perform a reset and disable watchdog. + jtag430_por(); + jtag430_writemem(0x120,0x5a80);//disable watchdog + + jtag430_haltcpu(); + + jtag430_resettap(); + txdata(app,verb,1); + + break; + case STOP: + jtag430_stop(); txdata(app,verb,0); break; case JTAG430_HALTCPU: @@ -310,13 +470,13 @@ void jtag430handle(unsigned char app, //Fetch large blocks for bulk fetches, //small blocks for individual peeks. if(len>5) - len=(cmddataword[2]);//always even. + l=(cmddataword[2]);//always even. else - len=2; - len&=~1;//clue lsbit + l=2; + l&=~1;//clear lsbit - txhead(app,verb,len); - for(i=0;i>1)-2;i++){ + //debugstr("Poking flash memory."); + jtag430_writeflash(at+(i<<1),cmddataword[i+2]); + //Reflash if needed. Try this twice to save grace? + if(cmddataword[i]!=jtag430_readmem(at)) + jtag430_writeflash(at+(i<<1),cmddataword[i+2]); + } + + //Return result of first write as a word. + cmddataword[0]=jtag430_readmem(cmddataword[0]); + txdata(app,verb,2); break; case JTAG430_ERASEFLASH: - jtag430_eraseflash(ERASE_MASS,0xFFFE,0x3000); + jtag430_eraseflash(ERASE_MASS,0xFFFE,0x3000,0); + txdata(app,verb,0); + break; + case JTAG430_ERASEINFO: + jtag430_eraseflash(ERASE_SGMT,0x1000,0x3000,1); txdata(app,verb,0); break; case JTAG430_SETPC: jtag430_haltcpu(); + //debughex("Setting PC."); + //debughex(cmddataword[0]); jtag430_setpc(cmddataword[0]); + jtag430_releasecpu(); txdata(app,verb,0); break; - + case JTAG430_SETREG: + jtag430_setr(cmddata[0],cmddataword[1]); + txdata(app,verb,0); + break; + case JTAG430_GETREG: + //jtag430_getr(cmddata[0]); + debugstr("JTAG430_GETREG not yet implemented."); + cmddataword[0]=0xDEAD; + txdata(app,verb,2); + break; case JTAG430_COREIP_ID: + cmddataword[0]=jtag430_coreid(); + txdata(app,verb,2); + break; case JTAG430_DEVICE_ID: - cmddataword[0]=0; - cmddataword[1]=0; + cmddatalong[0]=jtag430_deviceid(); txdata(app,verb,4); break; - default: - jtaghandle(app,verb,len); + (*(jtag_app.handle))(app,verb,len); } //jtag430_resettap(); //DO NOT UNCOMMENT }