X-Git-Url: http://git.rot13.org/?p=goodfet;a=blobdiff_plain;f=firmware%2Fapps%2Fjtag%2Fjtag430.c;h=d0b83cb526e80c13d4b79c0786801bae74fde9be;hp=081fb52427368ba49aa95e39d7d24850c8bb5dca;hb=f4a6b415e762bcdc560f3ea655851d16f483ea5a;hpb=7487b2cd89324081ccfc195d49f4158f10ec534f diff --git a/firmware/apps/jtag/jtag430.c b/firmware/apps/jtag/jtag430.c index 081fb52..d0b83cb 100644 --- a/firmware/apps/jtag/jtag430.c +++ b/firmware/apps/jtag/jtag430.c @@ -1,9 +1,15 @@ +/*! \file jtag430.c + \author Travis Goodspeed + \brief MSP430 JTAG (16-bit) +*/ #include "platform.h" #include "command.h" #include "jtag.h" +unsigned int jtag430mode=MSP430X2MODE; + //! Set the program counter. void jtag430_setpc(unsigned int adr){ jtag_ir_shift8(IR_CNTRL_SIG_16BIT); @@ -46,9 +52,11 @@ void jtag430_releasecpu(){ //! Read data from address unsigned int jtag430_readmem(unsigned int adr){ unsigned int toret; + jtag430_haltcpu(); CLRTCLK; jtag_ir_shift8(IR_CNTRL_SIG_16BIT); + if(adr>0xFF) jtag_dr_shift16(0x2409);//word read else @@ -79,31 +87,9 @@ void jtag430_writemem(unsigned int adr, unsigned int data){ SETTCLK; } -//! Defined in jtag430asm.S -void jtag430_tclk_flashpulses(int); -/* //! Pulse TCLK at 350kHz +/- 100kHz */ -/* void jtag430_tclk_flashpulses(register i){ */ -/* //TODO check this on a scope. */ -/* register j=0; */ - -/* //At 2MHz, 350kHz is obtained with 5 clocks of delay */ - -/* /\** Pondering: */ -/* What happens if the frequency is too low or to high? */ -/* Is there any risk of damaging the chip, or only of a poor write? */ -/* *\/ */ -/* while(j++!=i){ */ -/* SETTCLK; */ -/* _NOP(); */ -/* _NOP(); */ -/* _NOP(); */ -/* CLRTCLK; */ -/* } */ -/* } */ - //! Write data to flash memory. Must be preconfigured. void jtag430_writeflashword(unsigned int adr, unsigned int data){ - /* + CLRTCLK; jtag_ir_shift8(IR_CNTRL_SIG_16BIT); jtag_dr_shift16(0x2408);//word write @@ -117,16 +103,16 @@ void jtag430_writeflashword(unsigned int adr, unsigned int data){ CLRTCLK; jtag_ir_shift8(IR_CNTRL_SIG_16BIT); jtag_dr_shift16(0x2409); - */ + /* jtag430_writemem(adr,data); CLRTCLK; jtag_ir_shift8(IR_CNTRL_SIG_16BIT); jtag_dr_shift16(0x2409); + */ //Pulse TCLK jtag430_tclk_flashpulses(35); //35 standard - } //! Configure flash, then write a word. @@ -138,7 +124,7 @@ void jtag430_writeflash(unsigned int adr, unsigned int data){ //FCTL2=0xA540, selecting MCLK as source, DIV=1 jtag430_writemem(0x012A, 0xA540); //FCTL3=0xA500, should be 0xA540 for Info Seg A on 2xx chips. - jtag430_writemem(0x012C, 0xA500); + jtag430_writemem(0x012C, 0xA500); //all but info flash. //Write the word itself. jtag430_writeflashword(adr,data); @@ -146,7 +132,28 @@ void jtag430_writeflash(unsigned int adr, unsigned int data){ //FCTL1=0xA500, disabling flash write jtag430_writemem(0x0128, 0xA500); - jtag430_releasecpu(); + //jtag430_releasecpu(); +} + + + +//! Power-On Reset +void jtag430_por(){ + unsigned int jtagid; + + // Perform Reset + jtag_ir_shift8(IR_CNTRL_SIG_16BIT); + jtag_dr_shift16(0x2C01); // apply + jtag_dr_shift16(0x2401); // remove + CLRTCLK; + SETTCLK; + CLRTCLK; + SETTCLK; + CLRTCLK; + jtagid = jtag_ir_shift8(IR_ADDR_CAPTURE); // get JTAG identifier + SETTCLK; + + jtag430_writemem(0x0120, 0x5A80); // Diabled Watchdog } @@ -159,6 +166,8 @@ void jtag430_writeflash(unsigned int adr, unsigned int data){ //! Configure flash, then write a word. void jtag430_eraseflash(unsigned int mode, unsigned int adr, unsigned int count){ + jtag430_haltcpu(); + //FCTL1= erase mode jtag430_writemem(0x0128, mode); //FCTL2=0xA540, selecting MCLK as source, DIV=1 @@ -178,6 +187,8 @@ void jtag430_eraseflash(unsigned int mode, unsigned int adr, unsigned int count) //FCTL1=0xA500, disabling flash write jtag430_writemem(0x0128, 0xA500); + + //jtag430_releasecpu(); } @@ -185,8 +196,9 @@ void jtag430_eraseflash(unsigned int mode, unsigned int adr, unsigned int count) void jtag430_resettap(){ int i; // Settle output + SETTDI; //430X2 SETTMS; - SETTDI; + //SETTDI; //classic SETTCK; // Navigate to reset state. @@ -205,7 +217,7 @@ void jtag430_resettap(){ /* sacred, by spec. - Sometimes this isn't necessary. */ + Sometimes this isn't necessary. */ // fuse check CLRTMS; delay(50); @@ -229,18 +241,25 @@ void jtag430_start(){ //Entry sequence from Page 67 of SLAU265A for 4-wire MSP430 JTAG CLRRST; - delay(100); + delay(100); //100 CLRTST; - delay(50); + delay(50); //50 SETTST; - delay(50); + delay(50); //50 SETRST; P5DIR&=~RST; delay(0xFFFF); + + //Perform a reset and disable watchdog. + jtag430_por(); + jtag430_writemem(0x120,0x5a80);//disable watchdog + + jtag430_haltcpu(); } //! Set CPU to Instruction Fetch void jtag430_setinstrfetch(){ + jtag_ir_shift8(IR_CNTRL_SIG_CAPTURE); // Wait until instruction fetch state. @@ -252,17 +271,24 @@ void jtag430_setinstrfetch(){ } } -//! Handles unique MSP430 JTAG commands. Forwards others to JTAG. + +//! Handles classic MSP430 JTAG commands. Forwards others to JTAG. void jtag430handle(unsigned char app, unsigned char verb, - unsigned char len){ - unsigned char i; + unsigned long len){ + register char blocks; + unsigned long at; + unsigned int i, val; + + //debugstr("Classic MSP430 handler."); + switch(verb){ case START: //Enter JTAG mode. jtag430_start(); //TAP setup, fuse check jtag430_resettap(); + txdata(app,verb,0); break; case JTAG430_HALTCPU: @@ -277,37 +303,68 @@ void jtag430handle(unsigned char app, jtag430_setinstrfetch(); txdata(app,verb,0); break; - case JTAG430_READMEM: case PEEK: - cmddataword[0]=jtag430_readmem(cmddataword[0]); - txdata(app,verb,2); + at=cmddatalong[0]; + + //Fetch large blocks for bulk fetches, + //small blocks for individual peeks. + if(len>5) + len=(cmddataword[2]);//always even. + else + len=2; + len&=~1;//clue lsbit + + txhead(app,verb,len); + for(i=0;i>8); + } break; case JTAG430_WRITEMEM: case POKE: - jtag430_writemem(cmddataword[0],cmddataword[1]); + jtag430_haltcpu(); + jtag430_writemem(cmddataword[0],cmddataword[2]); cmddataword[0]=jtag430_readmem(cmddataword[0]); txdata(app,verb,2); break; case JTAG430_WRITEFLASH: - jtag430_writeflash(cmddataword[0],cmddataword[1]); + //debugstr("Poking flash memory."); + jtag430_writeflash(cmddataword[0],cmddataword[2]); + + //Try again if failure. + if(cmddataword[0]!=jtag430_readmem(cmddataword[0])) + jtag430_writeflash(cmddataword[0],cmddataword[2]); + + //Return result. cmddataword[0]=jtag430_readmem(cmddataword[0]); + txdata(app,verb,2); break; case JTAG430_ERASEFLASH: - jtag430_eraseflash(ERASE_MASS,0xFFFE,0xFFFF); - jtag430_eraseflash(ERASE_MASS,0xFFFE,0xFFFF); - jtag430_eraseflash(ERASE_MASS,0xFFFE,0xFFFF); + jtag430_eraseflash(ERASE_MASS,0xFFFE,0x3000); txdata(app,verb,0); break; case JTAG430_SETPC: + jtag430_haltcpu(); jtag430_setpc(cmddataword[0]); txdata(app,verb,0); break; + + case JTAG430_COREIP_ID: + case JTAG430_DEVICE_ID: + cmddataword[0]=0; + cmddataword[1]=0; + txdata(app,verb,4); + break; + default: jtaghandle(app,verb,len); } - jtag430_resettap(); + //jtag430_resettap(); //DO NOT UNCOMMENT } -