X-Git-Url: http://git.rot13.org/?p=goodfet;a=blobdiff_plain;f=firmware%2Fapps%2Fspi%2Fspi.c;h=f02d4022146479c4622f2edf15c5f23a3bfe36f5;hp=5e762050839135e5c4fc270bee9a95108e3f59a2;hb=78f4f21969789bec27a8e2957eb00a87d8756041;hpb=fd966b09563a102ed42b1613e7fa5e934eed2656

diff --git a/firmware/apps/spi/spi.c b/firmware/apps/spi/spi.c
index 5e76205..f02d402 100644
--- a/firmware/apps/spi/spi.c
+++ b/firmware/apps/spi/spi.c
@@ -1,5 +1,7 @@
-//GoodFET SPI Application
-//Handles basic I/O
+/*! \file spi.c
+  \author Travis Goodspeed
+  \brief SPI Master
+*/
 
 //Higher level left to client application.
 
@@ -10,36 +12,30 @@
 #include <io.h>
 #include <iomacros.h>
 
-
-//Pins and I/O
-#define SS   BIT0
-#define MOSI BIT1
-#define MISO BIT2
-#define SCK  BIT3
+#include <spi.h>
 
 //This could be more accurate.
 //Does it ever need to be?
 #define SPISPEED 0
-#define SPIDELAY(x) delay(x)
-
-#define SETMOSI P5OUT|=MOSI
-#define CLRMOSI P5OUT&=~MOSI
-#define SETCLK P5OUT|=SCK
-#define CLRCLK P5OUT&=~SCK
-#define READMISO (P5IN&MISO?1:0)
-
+#define SPIDELAY(x)
+//delay(x)
 
 
 //! Set up the pins for SPI mode.
-unsigned char spisetup(){
+void spisetup(){
+  P5OUT|=SS;
   P5DIR|=MOSI+SCK+SS;
   P5DIR&=~MISO;
+  
+  //Begin a new transaction.
+  P5OUT&=~SS; 
   P5OUT|=SS;
 }
 
-//! Read and write an SPI bit.
+
+//! Read and write an SPI byte.
 unsigned char spitrans8(unsigned char byte){
-  unsigned int bit;
+  register unsigned int bit;
   //This function came from the SPI Wikipedia article.
   //Minor alterations.
   
@@ -51,13 +47,8 @@ unsigned char spitrans8(unsigned char byte){
       CLRMOSI;
     byte <<= 1;
  
-    /* half a clock cycle before leading/rising edge */
-    SPIDELAY(SPISPEED/2);
     SETCLK;
- 
-    /* half a clock cycle before trailing/falling edge */
-    SPIDELAY(SPISPEED/2);
- 
+  
     /* read MISO on trailing edge */
     byte |= READMISO;
     CLRCLK;
@@ -66,24 +57,203 @@ unsigned char spitrans8(unsigned char byte){
   return byte;
 }
 
+
+//! Enable SPI writing
+void spiflash_wrten(){
+  SETSS;
+  /*
+  P5OUT&=~SS; //Drop !SS to begin transaction.
+  spitrans8(0x04);//Write Disable
+  P5OUT|=SS;  //Raise !SS to end transaction.
+  */
+  P5OUT&=~SS; //Drop !SS to begin transaction.
+  spitrans8(0x06);//Write Enable
+  P5OUT|=SS;  //Raise !SS to end transaction.
+}
+
+
+//! Grab the SPI flash status byte.
+unsigned char spiflash_status(){
+  unsigned char c;
+  P5OUT|=SS;  //Raise !SS to end transaction.
+  P5OUT&=~SS; //Drop !SS to begin transaction.
+  spitrans8(0x05);//GET STATUS
+  c=spitrans8(0xFF);
+  P5OUT|=SS;  //Raise !SS to end transaction.
+  return c;
+}
+
+
+//! Grab the SPI flash status byte.
+void spiflash_setstatus(unsigned char c){
+  SETSS;
+  CLRSS; //Drop !SS to begin transaction.
+  spitrans8(0x01);//SET STATUS
+  spitrans8(c);
+  SETSS;  //Raise !SS to end transaction.
+  //return c;
+}
+
+
+//! Read a block to a buffer.
+void spiflash_peekblock(unsigned long adr,
+			unsigned char *buf,
+			unsigned int len){
+  unsigned char i;
+  
+  SETSS;
+  CLRSS; //Drop !SS to begin transaction.
+  spitrans8(0x03);//Flash Read Command
+  
+  //Send address
+  spitrans8((adr&0xFF0000)>>16);
+  spitrans8((adr&0xFF00)>>8);
+  spitrans8(adr&0xFF);
+  
+  for(i=0;i<len;i++)
+    buf[i]=spitrans8(0);
+  SETSS;  //Raise !SS to end transaction.
+}
+
+//! Write many blocks to the SPI Flash.
+void spiflash_pokeblocks(unsigned long adr,
+			 unsigned char *buf,
+			 unsigned int len){
+  long off=0;//offset of this block
+  int blen;//length of this block
+  SETSS;
+  spiflash_setstatus(0x02);
+  spiflash_wrten();
+  
+  while(off<len){
+    //calculate block length
+    blen=(len-off>0x100?0x100:len-off);
+    //write the block
+    spiflash_pokeblock(adr+off,
+		       buf+off,
+		       blen);
+    //add offset
+    off+=blen;
+  }
+}
+
+//! Read a block to a buffer.
+void spiflash_pokeblock(unsigned long adr,
+			unsigned char *buf,
+			unsigned int len){
+  unsigned int i;
+  
+  SETSS;
+  
+  //while(spiflash_status()&0x01);//minor performance impact
+  
+  //Are these necessary?
+  //spiflash_setstatus(0x02);
+  //spiflash_wrten();
+  
+  CLRSS; //Drop !SS to begin transaction.
+  spitrans8(0x02); //Poke command.
+  
+  //Send address
+  spitrans8((adr&0xFF0000)>>16);
+  spitrans8((adr&0xFF00)>>8);
+  spitrans8(adr&0xFF);
+
+  for(i=0;i<len;i++)
+    spitrans8(buf[i]);
+  SETSS;  //Raise !SS to end transaction.
+  
+  while(spiflash_status()&0x01);//minor performance impact
+  return;
+}
+
+
+//! Peek some blocks.
+void spiflash_peek(unsigned char app,
+		   unsigned char verb,
+		   unsigned long len){
+  unsigned int i;
+  P5OUT&=~SS; //Drop !SS to begin transaction.
+  spitrans8(0x03);//Flash Read Command
+  len=3;//write 3 byte pointer
+  for(i=0;i<len;i++)
+    spitrans8(cmddata[i]);
+  
+  //Send reply header
+  len=0x1000;
+  txhead(app,verb,len);
+  
+  while(len--)
+    serial_tx(spitrans8(0));
+  
+  P5OUT|=SS;  //Raise !SS to end transaction.
+}
+
 //! Handles a monitor command.
 void spihandle(unsigned char app,
 	       unsigned char verb,
-	       unsigned char len){
-  unsigned char i;
+	       unsigned long len){
+  unsigned long i;
+  
+  //Raise !SS to end transaction, just in case we forgot.
+  P5OUT|=SS;
+  spisetup();
+  
   switch(verb){
     //PEEK and POKE might come later.
   case READ:
   case WRITE:
     P5OUT&=~SS; //Drop !SS to begin transaction.
+    for(i=0;i<len;i++)
+      cmddata[i]=spitrans8(cmddata[i]);
+    P5OUT|=SS;  //Raise !SS to end transaction.
+    txdata(app,verb,len);
+    break;
+
+
+  case SPI_JEDEC://Grab 3-byte JEDEC ID.
+    P5OUT&=~SS; //Drop !SS to begin transaction.
+    spitrans8(0x9f);
+    len=3;  //Length is variable in some chips, 3 minimum.
     for(i=0;i<len;i++)
       cmddata[i]=spitrans8(cmddata[i]);
     txdata(app,verb,len);
     P5OUT|=SS;  //Raise !SS to end transaction.
     break;
+
+
+  case PEEK://Grab 128 bytes from an SPI Flash ROM
+    spiflash_peek(app,verb,len);
+    break;
+
+
+  case POKE://Poke up bytes from an SPI Flash ROM.
+    spiflash_pokeblocks(cmddatalong[0],//adr
+			cmddata+4,//buf
+			len-4);//len    
+    
+    txdata(app,verb,len);
+    break;
+
+
+  case SPI_ERASE://Erase the SPI Flash ROM.
+    spiflash_wrten();
+    P5OUT&=~SS; //Drop !SS to begin transaction.
+    spitrans8(0xC7);//Chip Erase
+    P5OUT|=SS;  //Raise !SS to end transaction.
+    
+    
+    while(spiflash_status()&0x01)//while busy
+      P1OUT^=1;
+    P1OUT&=~1;
+    
+    txdata(app,verb,0);
+    break;
+
   case SETUP:
     spisetup();
     txdata(app,verb,0);
     break;
   }
+  
 }