X-Git-Url: http://git.rot13.org/?p=goodfet;a=blobdiff_plain;f=firmware%2Finclude%2Fchipcon.h;h=4b01b64ef06b9b291e772bc9ab2bd730382aea66;hp=dd96f81edad2958f63cfacc1c9001213a3c5a0b1;hb=a031b4a563978102c664466d1e91a9c3ab0553dd;hpb=7d3404539568650baef6a21c85580ea8e3e097aa

diff --git a/firmware/include/chipcon.h b/firmware/include/chipcon.h
index dd96f81..4b01b64 100644
--- a/firmware/include/chipcon.h
+++ b/firmware/include/chipcon.h
@@ -3,9 +3,18 @@
   \brief Chipcon application functions.
 */
 
+#ifndef CHIPCON_H
+#define CHIPCON_H
+
+#include "command.h"
+#include "app.h"
+
+#define CHIPCON 0x30
 
 //Chipcon command definitions.
 #define CCCMD_CHIP_ERASE 0x14
+
+//1D or 19?
 #define CCCMD_WR_CONFIG 0x1D
 #define CCCMD_RD_CONFIG 0x24
 #define CCCMD_READ_STATUS 0x34
@@ -16,6 +25,9 @@
 #define CCCMD_STEP_INSTR 0x5C
 #define CCCMD_DEBUG_INSTR 0x54
 
+//! Flash Word Size
+extern u8 flash_word_size;
+
 //! Erase a chipcon chip.
 void cc_chip_erase();
 //! Write the configuration byte.
@@ -36,6 +48,10 @@ void cc_debug_instr(unsigned char);
 unsigned char cc_peekcodebyte(unsigned long adr);
 //!Read a byte of data memory.
 unsigned char cc_peekdatabyte(unsigned int adr);
+//! Fetch a byte of IRAM.
+u8 cc_peekirambyte(u8 adr);
+//! Write a byte of IRAM.
+u8 cc_pokeirambyte(u8 adr, u8 val);
 //! Set a byte of data memory.
 unsigned char cc_pokedatabyte(unsigned int adr,
 			      unsigned char val);
@@ -45,13 +61,32 @@ unsigned char cc_debug(unsigned char len,
 		       unsigned char b,
 		       unsigned char c);
 
+//! Populates flash buffer in xdata.
+void cc_write_flash_buffer(u8 *data, u16 len);
+//! Populates flash buffer in xdata.
+void cc_write_xdata(u16 adr, u8 *data, u16 len);
+//! Copies flash buffer to flash.
+void cc_write_flash_page(u32 adr);
+//! Set the Chipcon's Program Counter
+void cc_set_pc(u32 adr);
+
 //! Halt the CPU.
 void cc_halt();
 //! Resume the CPU.
 void cc_resume();
 //! Step an instruction
 void cc_step_instr();
+//! Locks the chip.
+void cc_lockchip();
 
+#define CC_STATUS_ERASED 0x80
+#define CC_STATUS_PCONIDLE 0x40
+#define CC_STATUS_CPUHALTED 0x20
+#define CC_STATUS_PM0 0x10
+#define CC_STATUS_HALTSTATUS 0x08
+#define CC_STATUS_LOCKED 0x04
+#define CC_STATUS_OSCSTABLE 0x02
+#define CC_STATUS_OVERFLOW 0x01
 
 //CHIPCON commands
 #define CC_CHIP_ERASE 0x80
@@ -76,3 +111,9 @@ void cc_step_instr();
 #define CC_READ_FLASH_PAGE 0x96
 #define CC_MASS_ERASE_FLASH 0x97
 #define CC_PROGRAM_FLASH 0x98
+#define CC_WIPEFLASHBUFFER 0x99
+#define CC_LOCKCHIP 0x9A
+
+extern app_t const chipcon_app;
+
+#endif // CHIPCON_H