X-Git-Url: http://git.rot13.org/?p=goodfet;a=blobdiff_plain;f=firmware%2Finclude%2Fjtagarm7.h;h=74016a1fa8ee224dac6243dc1e09998dca0e9c31;hp=3c595550ae9c8546901aaae6a06da3ee2b9f1a51;hb=91c890ff97822d85543255c3f2bd76f2b1540f51;hpb=c3c1c0c873f693e6d57e8e2acf11d52aa6540ff3

diff --git a/firmware/include/jtagarm7.h b/firmware/include/jtagarm7.h
index 3c59555..74016a1 100644
--- a/firmware/include/jtagarm7.h
+++ b/firmware/include/jtagarm7.h
@@ -2,21 +2,33 @@
   \brief JTAG handler functions for the ARM7TDMI family of processors
 */
 
-#include "jtag.h"
+#ifndef JTAGARM7_H
+#define JTAGARM7_H
 
+#include "app.h"
+
+#define JTAGARM7 0x13
 
 #define JTAGSTATE_ARM 0         // bit 4 on dbg status reg is low
 #define JTAGSTATE_THUMB 1
 
-unsigned long last_instr = -1;
-unsigned char last_sysstate = 0;
-unsigned char last_ir = -1;
-unsigned char last_scanchain = -1;
-unsigned char tapstate = 15;
-unsigned char current_dbgstate = -1;
-//unsigned char last_halt_debug_state = -1;
-//unsigned long last_halt_pc = -1;
-
+// JTAG TAP states
+#define Exit2_DR 0x0
+#define Exit_DR 0x1
+#define Shift_DR 0x2
+#define Pause_DR 0x3
+#define Select_IR 0x4
+#define Update_DR 0x5
+#define Capture_DR 0x6
+#define Select_DR 0x7
+#define Exit2_IR 0x8
+#define Exit_IR 0x9
+#define Shift_IR 0xa
+#define Pause_IR 0xb
+#define RunTest_Idle 0xc
+#define Update_IR 0xd
+#define Capture_IR 0xe
+#define Test_Reset 0xf
 
 // JTAGARM7 Commands
 
@@ -28,6 +40,9 @@ void jtagarm7tdmi_set_register(unsigned long reg, unsigned long val);
 //!  Get a 32-bit ARM register
 unsigned long jtagarm7tdmi_get_register(unsigned long reg);
 
+//!  Shift an arbitrary number of bits, using an array of uchars
+uint8_t* jtag_trans_many(uint8_t *word, uint8_t bitcount, enum eTransFlags flags);
+
 // ARM7TDMI-specific pins
 // DBGRQ - GoodFET Pin 8
 #define DBGRQ   TST
@@ -90,9 +105,9 @@ The least significant bit of the instruction register is scanned in and scanned
 
 
 //JTAGARM7TDMI commands
-#define JTAGARM7_GET_REGISTER               0x87
-#define JTAGARM7_SET_REGISTER               0x88
-#define JTAGARM7_DEBUG_INSTR                0x89
+#define JTAGARM7_GET_REGISTER               0x8d
+#define JTAGARM7_SET_REGISTER               0x8e
+#define JTAGARM7_DEBUG_INSTR                0x8f
 // Really ARM specific stuff
 #define JTAGARM7_SET_IR                     0x90
 #define JTAGARM7_WAIT_DBG                   0x91
@@ -101,7 +116,11 @@ The least significant bit of the instruction register is scanned in and scanned
 #define JTAGARM7_SCANCHAIN1                 0x94
 #define JTAGARM7_EICE_READ                  0x95
 #define JTAGARM7_EICE_WRITE                 0x96
+#define JTAGARM7_IR_SIZE                    0x9f
+#define JTAGARM7_SCAN_N_SIZE                0x9e
 
+#define JTAGARM_SCAN1_MANY                  0x9d
+#define JTAG_DR_SHIFT_MANY                  0x9c
 
 // for deeper understanding, read the instruction cycle timing section of: 
 //      http://www.atmel.com/dyn/resources/prod_documents/DDI0029G_7TDMI_R3_trm.pdf
@@ -144,4 +163,9 @@ The least significant bit of the instruction register is scanned in and scanned
 #define JTAG_ARM7TDMI_DBG_IFEN      4
 #define JTAG_ARM7TDMI_DBG_cgenL     8
 #define JTAG_ARM7TDMI_DBG_TBIT      16
+extern app_t const jtagarm7_app;
+extern unsigned char g_jtag_ir_size;
+extern unsigned char g_jtagarm_scan_n_bitsize;
+
+#endif // JTAGARM7_H