X-Git-Url: http://git.rot13.org/?p=goodfet;a=blobdiff_plain;f=firmware%2Finclude%2Fjtagarm7tdmi.h;h=c17ac937ab04bc19fc20c297d50378b761292f0e;hp=7475117bd4f3250da285ddc86bd5107fff6ea8bb;hb=4f46215fbc6ac9d774a4c56e17398b548d057ba5;hpb=714cff0c45e9987edee5595f0c3bdc9f3e96360a

diff --git a/firmware/include/jtagarm7tdmi.h b/firmware/include/jtagarm7tdmi.h
index 7475117..c17ac93 100644
--- a/firmware/include/jtagarm7tdmi.h
+++ b/firmware/include/jtagarm7tdmi.h
@@ -1,5 +1,4 @@
 /*! \file jtagarm7tdmi.h
-  \author Matthew Carpenter <matt@inguardians.com>
   \brief JTAG handler functions for the ARM7TDMI family of processors
 */
 
@@ -16,7 +15,6 @@
 
 
 
-unsigned long registers[16];   // constant array 
 unsigned char current_chain;
 unsigned char last_halt_debug_state = -1;
 unsigned long last_halt_pc = -1;
@@ -43,7 +41,7 @@ unsigned long jtagarm7tdmi_haltcpu();
 unsigned long jtagarm7tdmi_releasecpu();
 
 //! Set the program counter.
-unsigned long jtagarm7tdmi_setpc(unsigned long adr);
+void jtagarm7tdmi_setpc(unsigned long adr);
 
 //! Write data to address.
 unsigned long jtagarm7tdmi_writeflash(unsigned long adr, unsigned long data);
@@ -171,27 +169,30 @@ The least significant bit of the instruction register is scanned in and scanned
 
 // for deeper understanding, read the instruction cycle timing section of: 
 //      http://www.atmel.com/dyn/resources/prod_documents/DDI0029G_7TDMI_R3_trm.pdf
-#define EXECNOPARM                  0xe1a00000
-#define ARM_INSTR_NOP               0xe1a00000
-#define ARM_INSTR_STR_Rx_r14        0xe58e0000
+#define EXECNOPARM                  0xe1a00000L
+#define ARM_INSTR_NOP               0xe1a00000L
+#define ARM_INSTR_STR_Rx_r14        0xe58e0000L // from atmel docs
+//#define ARM_INSTR_STR_Rx_r14        0xe5800000L // set both src and dest reg in code
 #define ARM_READ_REG                ARM_INSTR_STR_Rx_r14
-#define ARM_INSTR_LDR_Rx_r14        0xe59e0000
+#define ARM_INSTR_LDR_Rx_r14        0xe59e0000L // from atmel docs
+//#define ARM_INSTR_LDR_Rx_r14        0xe5900000L // set both src and dest reg in code
 #define ARM_WRITE_REG               ARM_INSTR_LDR_Rx_r14
-#define ARM_INSTR_LDR_R1_r0_4       0xe4901004
+#define ARM_INSTR_LDR_R1_r0_4       0xe4901004L
 #define ARM_READ_MEM                ARM_INSTR_LDR_R1_r0_4
-#define ARM_INSTR_MRS_R0_CPSR       0xf10f0000
-#define ARM_INSTR_MSR_cpsr_cxsf_R0  0xe12ff000
-#define ARM_INSTR_STM_R0_r0_r15     0x 
-#define ARM_INSTR_STMIA_R14_r0_rx   0xE88E0000      // add up to 65k to indicate which registers...
-#define ARM_INSTR_SKANKREGS         0xE88Effff      // add up to 65k to indicate which registers...
+#define ARM_INSTR_MRS_R0_CPSR       0xf10f0000L
+#define ARM_INSTR_MSR_cpsr_cxsf_R0  0xe12ff000L
+#define ARM_INSTR_STMIA_R14_r0_rx   0xE88E0000L      // add up to 65k to indicate which registers...
 #define ARM_STORE_MULTIPLE          ARM_INSTR_STMIA_R14_r0-rx
-
-#define ARM_INSTR_B_PC              0xea000000
-#define ARM_INSTR_BX_PC             0xe1200010      // need to set r0 to the desired address
-#define THUMB_INSTR_STR_R0_r0       0x60006000
-#define THUMB_INSTR_MOV_R0_PC       0x46b846b8
-#define THUMB_INSTR_BX_PC           0x47784778
-#define THUMB_INSTR_NOP             0x1c001c00
+#define ARM_INSTR_SKANKREGS1        0xE88E00ffL
+#define ARM_INSTR_SKANKREGS2        0xE88Eff00L
+#define ARM_INSTR_CLOBBEREGS        0xE89EffffL
+
+#define ARM_INSTR_B_PC              0xea000000L
+#define ARM_INSTR_BX_PC             0xe1200010L      // need to set r0 to the desired address
+#define THUMB_INSTR_STR_R0_r0       0x60006000L
+#define THUMB_INSTR_MOV_R0_PC       0x46b846b8L
+#define THUMB_INSTR_BX_PC           0x47784778L
+#define THUMB_INSTR_NOP             0x1c001c00L
 #define ARM_REG_PC                  15
 
 #define JTAG_ARM7TDMI_DBG_DBGACK    1