X-Git-Url: http://git.rot13.org/?p=goodfet;a=blobdiff_plain;f=firmware%2Flib%2Fmsp430x1612.c;h=9d284157eea3f5e76a2061261fe46992ea42d8c3;hp=e69d209e68ca75b883ae4fcf415ddbdd7dd8f147;hb=5ac4c1769e9976b39e919bb5f5ac9e97f62e7d0f;hpb=e7fc7a31eae7b7c308c25580fd522d242caf4d3f

diff --git a/firmware/lib/msp430x1612.c b/firmware/lib/msp430x1612.c
index e69d209..9d28415 100644
--- a/firmware/lib/msp430x1612.c
+++ b/firmware/lib/msp430x1612.c
@@ -6,9 +6,8 @@
 #include <io.h>
 #include <iomacros.h>
 
-
 //! Receive a byte.
-unsigned char serial_rx(){
+unsigned char serial0_rx(){
   char c;
   
   while(!(IFG1&URXIFG0));//wait for a byte
@@ -31,9 +30,8 @@ unsigned char serial1_rx(){
   return c;
 }
 
-
 //! Transmit a byte.
-void serial_tx(unsigned char x){
+void serial0_tx(unsigned char x){
   while ((IFG1 & UTXIFG0) == 0); //loop until buffer is free
   TXBUF0 = x;
 }
@@ -44,8 +42,16 @@ void serial1_tx(unsigned char x){
   TXBUF1 = x;
 }
 
+/** Later, add support for the EZ430/FETUIF with 12MHz crystal
+    UBR00=0xE2; UBR10=0x04; UMCTL0=0x00; // uart0 12000000Hz 9600bps
+    UBR00=0x71; UBR10=0x02; UMCTL0=0x00; // uart0 12000000Hz 19200bps
+    UBR00=0x38; UBR10=0x01; UMCTL0=0x55; // uart0 12000000Hz 38400bps
+    UBR00=0xD0; UBR10=0x00; UMCTL0=0x4A; // uart0 12000000Hz 57581bps
+    UBR00=0x68; UBR10=0x00; UMCTL0=0x04; // uart0 12000000Hz 115273bps
+ */
+
 //! Set the baud rate.
-void setbaud(unsigned char rate){
+void setbaud0(unsigned char rate){
   
   //http://mspgcc.sourceforge.net/baudrate.html
   switch(rate){
@@ -70,31 +76,29 @@ void setbaud(unsigned char rate){
 
 //! Set the baud rate of the second uart.
 void setbaud1(unsigned char rate){
-  
   //http://mspgcc.sourceforge.net/baudrate.html
   switch(rate){
   case 1://9600 baud
-    //    UBR01=0x7F; UBR11=0x01; UMCTL1=0x5B; /* uart0 3683400Hz 9599bps */
+    UBR01=0x7F; UBR11=0x01; UMCTL1=0x5B; /* uart0 3683400Hz 9599bps */
     break;
   case 2://19200 baud
-    //UBR01=0xBF; UBR11=0x00; UMCTL1=0xF7; /* uart0 3683400Hz 19194bps */
+    UBR01=0xBF; UBR11=0x00; UMCTL1=0xF7; /* uart0 3683400Hz 19194bps */
     break;
   case 3://38400 baud
-    //UBR01=0x5F; UBR11=0x00; UMCTL1=0xBF; /* uart0 3683400Hz 38408bps */
+    UBR01=0x5F; UBR11=0x00; UMCTL1=0xBF; /* uart0 3683400Hz 38408bps */
     break;
   case 4://57600 baud
-    //UBR01=0x40; UBR11=0x00; UMCTL1=0x00; /* uart0 3683400Hz 57553bps */
+    UBR01=0x40; UBR11=0x00; UMCTL1=0x00; /* uart0 3683400Hz 57553bps */
     break;
   default:
   case 5://115200 baud
-    //UBR01=0x20; UBR11=0x00; UMCTL1=0x00; /* uart0 3683400Hz 115106bps */
+    UBR01=0x20; UBR11=0x00; UMCTL1=0x00; /* uart0 3683400Hz 115106bps */
     break;
   }
 }
 
 
-void msp430_init_uart(){
-  
+void msp430_init_uart0(){
   /* RS232 */
   
   P3SEL |= BIT4|BIT5;                        // P3.4,5 = USART0 TXD/RXD
@@ -103,7 +107,7 @@ void msp430_init_uart(){
   UCTL0 = SWRST | CHAR;                 /* 8-bit character, UART mode */
   UTCTL0 = SSEL1;                       /* UCLK = MCLK */
   
-  setbaud(0);
+  setbaud0(0);
   
   ME1 &= ~USPIE0;			/* USART1 SPI module disable */
   ME1 |= (UTXE0 | URXE0);               /* Enable USART1 TXD/RXD */
@@ -118,6 +122,55 @@ void msp430_init_uart(){
 }
 
 
+void msp430_init_uart1(){
+  
+  /* RS232 */
+  P3DIR &= ~0x80;			/* Select P37 for input (UART1RX) */
+  P3DIR |= 0x40;			/* Select P36 for output (UART1TX) */
+  P3SEL |= 0xC0;			/* Select P36,P37 for UART1{TX,RX} */
+  
+  UCTL1 = SWRST | CHAR;                 /* 8-bit character, UART mode */
+  UTCTL1 = SSEL1;                       /* UCLK = MCLK */
+  
+  setbaud1(0);
+  
+  ME2 &= ~USPIE1;			/* USART1 SPI module disable */
+  ME2 |= (UTXE1 | URXE1);               /* Enable USART1 TXD/RXD */
+
+  UCTL1 &= ~SWRST;
+
+  /* XXX Clear pending interrupts before enable!!! */
+  U1TCTL |= URXSE;
+
+  //IE2 |= URXIE1;                        /* Enable USART1 RX interrupt  */
+}
+
+
+/** For EZ430/FETUIF
+ void msp430_init_dco() {
+  WDTCTL = WDTPW + WDTHOLD; //stop WDT
+
+  BCSCTL1 = 0;
+
+  do {
+    int i;
+    IFG1 &= ~OFIFG;
+    for (i=0; i<1000; i++);
+
+  } while (IFG1 & OFIFG);
+
+  BCSCTL2 = SELM1 | DIVM1 | SELS;
+
+}
+ */
+
+
+//! Initialization is correct.
+void msp430_init_dco_done(){
+  //Nothing to do for the 1612.
+}
+
+
 void msp430_init_dco() {
 /* This code taken from the FU Berlin sources and reformatted. */
   //
@@ -129,7 +182,7 @@ void msp430_init_dco() {
 //#define MSP430_CPU_SPEED 4915200UL
 
 //Max speed.
-//#deefine MSP430_CPU_SPEED 4500000UL
+//#define MSP430_CPU_SPEED 4500000UL
 
 //baud rate speed
 #define MSP430_CPU_SPEED 3683400UL
@@ -151,7 +204,7 @@ void msp430_init_dco() {
   BCSCTL2 = 0x00; /* Init FLL to desired frequency using the 32762Hz
 		     crystal DCO frquenzy = 2,4576 MHz  */
   
-  P1OUT|=1;
+  PLEDOUT|=PLEDPIN;
   
   BCSCTL1 |= DIVA1 + DIVA0;             /* ACLK = LFXT1CLK/8 */
   for(i = 0xffff; i > 0; i--) {         /* Delay for XTAL to settle */
@@ -191,7 +244,7 @@ void msp430_init_dco() {
 
   BCSCTL1 &= ~(DIVA1 + DIVA0);          /* remove /8 divisor from ACLK again */
   
-  P1OUT=0;
+  PLEDOUT=~PLEDPIN;
 
 }