X-Git-Url: http://git.rot13.org/?p=goodfet;a=blobdiff_plain;f=firmware%2Flib%2Fmsp430x2618.c;h=ed437d75d6ef03b9406b080cff45c7c3e1d510df;hp=0158082eb4cf6e447b0fddf4c919d4b670e89432;hb=e7cf01821d7a9e56776b7e48202253d3679ea475;hpb=4ad169e89a063394cbc38963eba6fdd0b52ceba4 diff --git a/firmware/lib/msp430x2618.c b/firmware/lib/msp430x2618.c index 0158082..ed437d7 100644 --- a/firmware/lib/msp430x2618.c +++ b/firmware/lib/msp430x2618.c @@ -1,7 +1,6 @@ //! MSP430F2618 clock and I/O definitions -// Ought to be portable to other 2xx chips. -// 2274 looks particularly appealing. +// Included by other 2xx ports, such as the 2274. #include "platform.h" @@ -103,36 +102,54 @@ void setbaud1(unsigned char rate){ void msp430_init_uart(){ - // Serial on P3.4, P3.5 + // Serial on P3.4, P3.5 P3SEL |= BIT4 + BIT5; P3DIR |= BIT4; - //UCA0CTL1 |= UCSWRST; /* disable UART */ + //UCA0CTL1 |= UCSWRST; /* disable UART */ UCA0CTL0 = 0x00; - //UCA0CTL0 |= UCMSB ; - UCA0CTL1 |= UCSSEL_2; // SMCLK + //UCA0CTL0 |= UCMSB ; - //UCA0BR0 = BAUD0EN; // 115200 + UCA0CTL1 |= UCSSEL_2; // SMCLK + + //UCA0BR0 = BAUD0EN; // 115200 //UCA0BR1 = BAUD1EN; setbaud(5);//default baud, 115200 - UCA0MCTL = 0; // Modulation UCBRSx = 5 - UCA0CTL1 &= ~UCSWRST; // **Initialize USCI state machine** - + UCA0MCTL = 0; // Modulation UCBRSx = 5 + UCA0CTL1 &= ~UCSWRST; // **Initialize USCI state machine** - //Leave this commented! - //Interrupt is handled by target code, not by bootloader. - //IE2 |= UCA0RXIE; + //Leave this commented! + //Interrupt is handled by target code, not by bootloader. + //IE2 |= UCA0RXIE; } +//! Initialize the MSP430 clock. void msp430_init_dco() { - //This REQUIRES that info flash be unmolested. - //TODO check for that. + if(CALBC1_16MHZ!=0xFF){ + //Info is intact, use it. + BCSCTL1 = CALBC1_16MHZ; + DCOCTL = CALDCO_16MHZ; + }else{ + //Info is missing, guess at a good value. + switch(*((int*)0xff0)){ + default: + case 0x6ff2: //f26f, the MSP430F2618 + DCOCTL = 0x00; + #ifndef DCOVAL + #define DCOVAL 0x8f + #endif + BCSCTL1 = DCOVAL; //CALBC1_16MHZ at 0x10f9 + /** Observed DCOCTL values: + 2618: 7f, 97 + */ + DCOCTL = 0x83; //CALDCO_16MHZ at 0x10f8 + break; + } + } - BCSCTL1 = CALBC1_16MHZ; - DCOCTL = CALDCO_16MHZ; return; }