Changed default baud rate to 115200.
Properly calculated the flash-memory TCLK pulses.
The LED will light while the clock is calibrating, then dim once calibrated.
git-svn-id: https://svn.code.sf.net/p/goodfet/code/trunk@47
12e2690d-a6be-4b82-a7b7-
67c4a43b65c8
+//! Power-On Reset
+void jtag430_por(){
+ unsigned int jtagid;
+
+ // Perform Reset
+ jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
+ jtag_dr_shift16(0x2C01); // apply
+ jtag_dr_shift16(0x2401); // remove
+ CLRTCLK;
+ SETTCLK;
+ CLRTCLK;
+ SETTCLK;
+ CLRTCLK;
+ jtagid = jtag_ir_shift8(IR_ADDR_CAPTURE); // get JTAG identifier
+ SETTCLK;
+
+ jtag430_writemem(0x0120, 0x5A80); // Diabled Watchdog
+}
+
#define ERASE_GLOB 0xA50E
#define ERASE_GLOB 0xA50E
//! Configure flash, then write a word.
void jtag430_eraseflash(unsigned int mode, unsigned int adr, unsigned int count){
//! Configure flash, then write a word.
void jtag430_eraseflash(unsigned int mode, unsigned int adr, unsigned int count){
//FCTL1= erase mode
jtag430_writemem(0x0128, mode);
//FCTL2=0xA540, selecting MCLK as source, DIV=1
//FCTL1= erase mode
jtag430_writemem(0x0128, mode);
//FCTL2=0xA540, selecting MCLK as source, DIV=1
//FCTL1=0xA500, disabling flash write
jtag430_writemem(0x0128, 0xA500);
//FCTL1=0xA500, disabling flash write
jtag430_writemem(0x0128, 0xA500);
+
+ jtag430_releasecpu();
SETRST;
P5DIR&=~RST;
delay(0xFFFF);
SETRST;
P5DIR&=~RST;
delay(0xFFFF);
+
+ //Perform a reset and disable watchdog.
+ jtag430_por();
}
//! Set CPU to Instruction Fetch
}
//! Set CPU to Instruction Fetch
.globl jtag430_tclk_flashpulses
.type jtag430_tclk_flashpulses,@function /* declare main as a function */
.globl jtag430_tclk_flashpulses
.type jtag430_tclk_flashpulses,@function /* declare main as a function */
+
+
+//! At 3.68MHz, 7 to 14 cycles/loop are allowed for 257 to 475kHz
jtag430_tclk_flashpulses:
jtag430_tclk_flashpulses:
- sub #1, r15
- bis.b #2, &0x0031 ;SETTCLK
- nop
- nop
- nop
- bic.b #2, &0x0031 ;CLRTCLK
- tst r15
- jnz jtag430_tclk_flashpulses
+ mov #0x0031, r14
+pulseloop:
+ bis.b #2, @r14 ;SETTCLK, 3 cycles
+ sub #1, r15 ; 1 cycle
+ ;; 1+3+3+1+2=10, within limits
+ bic.b #2, @r14 ;CLRTCLK, 3 cycles
+ tst r15 ; 1 cycle
+ jnz pulseloop ; 2 cycles
//http://mspgcc.sourceforge.net/baudrate.html
switch(rate){
//http://mspgcc.sourceforge.net/baudrate.html
switch(rate){
- UBR00=0x00; UBR10=0x01; UMCTL0=0x00;
+ UBR00=0x7F; UBR10=0x01; UMCTL0=0x5B; /* uart0 3683400Hz 9599bps */
break;
case 2://19200 baud
break;
case 2://19200 baud
- UBR00=0x00; UBR10=0x02; UMCTL0=0x00;
+ UBR00=0xBF; UBR10=0x00; UMCTL0=0xF7; /* uart0 3683400Hz 19194bps */
break;
case 3://38400 baud
break;
case 3://38400 baud
- UBR00=0x40; UBR10=0x00; UMCTL0=0x00;
+ UBR00=0x5F; UBR10=0x00; UMCTL0=0xBF; /* uart0 3683400Hz 38408bps */
+ UBR00=0x40; UBR10=0x00; UMCTL0=0x00; /* uart0 3683400Hz 57553bps */
+ break;
+ default:
+ UBR00=0x20; UBR10=0x00; UMCTL0=0x00; /* uart0 3683400Hz 115106bps */
void msp430_init_dco() {
/* This code taken from the FU Berlin sources and reformatted. */
void msp430_init_dco() {
/* This code taken from the FU Berlin sources and reformatted. */
-#define MSP430_CPU_SPEED 2457600UL
+ //
+
+//Works well.
+//#define MSP430_CPU_SPEED 2457600UL
+
+//Too fast for internal resistor.
+//#define MSP430_CPU_SPEED 4915200UL
+
+//Max speed.
+//#deefine MSP430_CPU_SPEED 4500000UL
+
+//baud rate speed
+#define MSP430_CPU_SPEED 3683400UL
#define DELTA ((MSP430_CPU_SPEED) / (32768 / 8))
unsigned int compare, oldcapture = 0;
unsigned int i;
WDTCTL = WDTPW + WDTHOLD; //stop WDT
#define DELTA ((MSP430_CPU_SPEED) / (32768 / 8))
unsigned int compare, oldcapture = 0;
unsigned int i;
WDTCTL = WDTPW + WDTHOLD; //stop WDT
-
- BCSCTL1 = 0xa4; /* ACLK is devided by 4. RSEL=6 no division for MCLK
+
+
+ DCOCTL=0xF0;
+ //a4
+ //1100
+ BCSCTL1 = 0xa8; /* ACLK is devided by 4. RSEL=6 no division for MCLK
and SSMCLK. XT2 is off. */
BCSCTL2 = 0x00; /* Init FLL to desired frequency using the 32762Hz
crystal DCO frquenzy = 2,4576 MHz */
and SSMCLK. XT2 is off. */
BCSCTL2 = 0x00; /* Init FLL to desired frequency using the 32762Hz
crystal DCO frquenzy = 2,4576 MHz */
BCSCTL1 |= DIVA1 + DIVA0; /* ACLK = LFXT1CLK/8 */
for(i = 0xffff; i > 0; i--) { /* Delay for XTAL to settle */
asm("nop");
BCSCTL1 |= DIVA1 + DIVA0; /* ACLK = LFXT1CLK/8 */
for(i = 0xffff; i > 0; i--) { /* Delay for XTAL to settle */
asm("nop");
/* -> Select next higher RSEL */
}
}
/* -> Select next higher RSEL */
}
}
CCTL2 = 0; /* Stop CCR2 function */
TACTL = 0; /* Stop Timer_A */
BCSCTL1 &= ~(DIVA1 + DIVA0); /* remove /8 divisor from ACLK again */
CCTL2 = 0; /* Stop CCR2 function */
TACTL = 0; /* Stop Timer_A */
BCSCTL1 &= ~(DIVA1 + DIVA0); /* remove /8 divisor from ACLK again */
CC=msp430-gcc -g -mmcu=$(mcu) -DGCC $(GCCINC) -I ../../include
CC=msp430-gcc -g -mmcu=$(mcu) -DGCC $(GCCINC) -I ../../include
+all: $(app).hex
+$(app).hex: $(app)
+ msp430-objcopy $(app) -O ihex $(app).hex
install: $(app)
$(BSL) -e -p $(app)
#$(BSL) -P $(app) -g 0x2500
install: $(app)
$(BSL) -e -p $(app)
#$(BSL) -P $(app) -g 0x2500