Reclocked to 3.6834 MHz, exactly twice a standard PC uart.

Changed default baud rate to 115200.
Properly calculated the flash-memory TCLK pulses.
The LED will light while the clock is calibrating, then dim once calibrated.

git-svn-id: https://svn.code.sf.net/p/goodfet/code/trunk@47 12e2690d-a6be-4b82-a7b7-67c4a43b65c8

diff --git a/firmware/apps/jtag/jtag430.c b/firmware/apps/jtag/jtag430.c
index 081fb52..f805a4d 100644 (file)
--- a/firmware/apps/jtag/jtag430.c
+++ b/firmware/apps/jtag/jtag430.c
@@ -149,6 +149,25 @@ void jtag430_writeflash(unsigned int adr, unsigned int data){
   jtag430_releasecpu();
 }
 
+//! Power-On Reset
+void jtag430_por(){
+  unsigned int jtagid;
+
+  // Perform Reset
+  jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
+  jtag_dr_shift16(0x2C01); // apply
+  jtag_dr_shift16(0x2401); // remove
+  CLRTCLK;
+  SETTCLK;
+  CLRTCLK;
+  SETTCLK;
+  CLRTCLK;
+  jtagid = jtag_ir_shift8(IR_ADDR_CAPTURE); // get JTAG identifier
+  SETTCLK;
+  
+  jtag430_writemem(0x0120, 0x5A80);   // Diabled Watchdog
+}
+
 
 
 #define ERASE_GLOB 0xA50E
@@ -159,6 +178,8 @@ void jtag430_writeflash(unsigned int adr, unsigned int data){
 
 //! Configure flash, then write a word.
 void jtag430_eraseflash(unsigned int mode, unsigned int adr, unsigned int count){
+  jtag430_haltcpu();
+  
   //FCTL1= erase mode
   jtag430_writemem(0x0128, mode);
   //FCTL2=0xA540, selecting MCLK as source, DIV=1
@@ -178,6 +199,8 @@ void jtag430_eraseflash(unsigned int mode, unsigned int adr, unsigned int count)
   
   //FCTL1=0xA500, disabling flash write
   jtag430_writemem(0x0128, 0xA500);
+  
+  jtag430_releasecpu();
 }
 
 
@@ -237,6 +260,9 @@ void jtag430_start(){
   SETRST;
   P5DIR&=~RST;
   delay(0xFFFF);
+  
+  //Perform a reset and disable watchdog.
+  jtag430_por();
 }
 
 //! Set CPU to Instruction Fetch

diff --git a/firmware/apps/jtag/jtag430asm.S b/firmware/apps/jtag/jtag430asm.S
index 2477016..5c7caa2 100644 (file)
--- a/firmware/apps/jtag/jtag430asm.S
+++ b/firmware/apps/jtag/jtag430asm.S
@@ -1,14 +1,16 @@
 .globl jtag430_tclk_flashpulses
 .type jtag430_tclk_flashpulses,@function    /* declare main as a function */
-       
+
+
+//! At 3.68MHz, 7 to 14 cycles/loop are allowed for 257 to 475kHz
 jtag430_tclk_flashpulses:
-       sub #1, r15
-       bis.b #2, &0x0031       ;SETTCLK
-       nop
-       nop
-       nop
-       bic.b #2, &0x0031       ;CLRTCLK
-       tst r15
-       jnz jtag430_tclk_flashpulses
+       mov #0x0031, r14
+pulseloop:     
+       bis.b #2, @r14          ;SETTCLK, 3 cycles
+       sub #1, r15             ; 1 cycle
+       ;;  1+3+3+1+2=10, within limits
+       bic.b #2, @r14          ;CLRTCLK, 3 cycles
+       tst r15                 ; 1 cycle
+       jnz pulseloop           ; 2 cycles
        ret
 

diff --git a/firmware/lib/msp430f1612.c b/firmware/lib/msp430f1612.c
index fb6c4c0..c29a485 100644 (file)
--- a/firmware/lib/msp430f1612.c
+++ b/firmware/lib/msp430f1612.c
@@ -29,20 +29,21 @@ void setbaud(unsigned char rate){
   
   //http://mspgcc.sourceforge.net/baudrate.html
   switch(rate){
-  default:
-  case 0:
   case 1://9600 baud
-    UBR00=0x00; UBR10=0x01; UMCTL0=0x00;
+    UBR00=0x7F; UBR10=0x01; UMCTL0=0x5B; /* uart0 3683400Hz 9599bps */
     break;
   case 2://19200 baud
-    UBR00=0x00; UBR10=0x02; UMCTL0=0x00;
+    UBR00=0xBF; UBR10=0x00; UMCTL0=0xF7; /* uart0 3683400Hz 19194bps */
     break;
   case 3://38400 baud
-    UBR00=0x40; UBR10=0x00; UMCTL0=0x00;
+    UBR00=0x5F; UBR10=0x00; UMCTL0=0xBF; /* uart0 3683400Hz 38408bps */
     break;
-  //TODO
   case 4://57600 baud
+    UBR00=0x40; UBR10=0x00; UMCTL0=0x00; /* uart0 3683400Hz 57553bps */
+    break;
+  default:
   case 5://115200 baud
+    UBR00=0x20; UBR10=0x00; UMCTL0=0x00; /* uart0 3683400Hz 115106bps */
     break;
   }
 }
@@ -74,19 +75,37 @@ void msp430_init_uart(){
 
 void msp430_init_dco() {
     /* This code taken from the FU Berlin sources and reformatted. */
-#define MSP430_CPU_SPEED 2457600UL
+  //
+
+//Works well.
+//#define MSP430_CPU_SPEED 2457600UL
+
+//Too fast for internal resistor.
+//#define MSP430_CPU_SPEED 4915200UL
+
+//Max speed.
+//#deefine MSP430_CPU_SPEED 4500000UL
+
+//baud rate speed
+#define MSP430_CPU_SPEED 3683400UL
 #define DELTA    ((MSP430_CPU_SPEED) / (32768 / 8))
   unsigned int compare, oldcapture = 0;
   unsigned int i;
   
   WDTCTL = WDTPW + WDTHOLD; //stop WDT
-
-  BCSCTL1 = 0xa4; /* ACLK is devided by 4. RSEL=6 no division for MCLK
+  
+  
+  DCOCTL=0xF0;
+  //a4
+  //1100
+  BCSCTL1 = 0xa8; /* ACLK is devided by 4. RSEL=6 no division for MCLK
                     and SSMCLK. XT2 is off. */
 
   BCSCTL2 = 0x00; /* Init FLL to desired frequency using the 32762Hz
                     crystal DCO frquenzy = 2,4576 MHz  */
-
+  
+  P1OUT|=1;
+  
   BCSCTL1 |= DIVA1 + DIVA0;             /* ACLK = LFXT1CLK/8 */
   for(i = 0xffff; i > 0; i--) {         /* Delay for XTAL to settle */
     asm("nop");
@@ -119,10 +138,12 @@ void msp430_init_dco() {
                                         /* -> Select next higher RSEL  */
     }
   }
-
+  
   CCTL2 = 0;                            /* Stop CCR2 function */
   TACTL = 0;                            /* Stop Timer_A */
 
   BCSCTL1 &= ~(DIVA1 + DIVA0);          /* remove /8 divisor from ACLK again */
+  
+  P1OUT=0;
 }
 

diff --git a/firmware/tests/blink/Makefile b/firmware/tests/blink/Makefile
index 4b176de..85a9828 100644 (file)
--- a/firmware/tests/blink/Makefile
+++ b/firmware/tests/blink/Makefile
@@ -9,8 +9,13 @@ GCCINC=-T ../../ldscripts/161x.x
 CC=msp430-gcc -g -mmcu=$(mcu) -DGCC $(GCCINC) -I ../../include
 
 
+
+
 app=blink
 
+all: $(app).hex
+$(app).hex: $(app)
+       msp430-objcopy $(app) -O ihex $(app).hex
 install: $(app)
        $(BSL) -e -p $(app) 
        #$(BSL) -P $(app) -g 0x2500