EM260 SPI support. Really needs to be cleaned up.

git-svn-id: https://svn.code.sf.net/p/goodfet/code/trunk@661 12e2690d-a6be-4b82-a7b7-67c4a43b65c8

diff --git a/firmware/apps/spi/spi.c b/firmware/apps/spi/spi.c
index 98ff8f7..c533a74 100644 (file)
--- a/firmware/apps/spi/spi.c
+++ b/firmware/apps/spi/spi.c
@@ -54,7 +54,6 @@ unsigned char spitrans8(unsigned char byte){
     byte |= READMISO;
     CLRCLK;
   }
-  
   return byte;
 }
 
@@ -220,6 +219,21 @@ void spiflash_erasesector(unsigned long adr){
 }
 
 
+//! Wake an EM260 Radio
+void em260_wake(){
+  //debugstr("Waking EM260.");
+  #define RST BIT6
+  P2DIR|=RST;
+  SETRST;
+  delay(1024);
+  
+  CLRRST;//Wake chip.
+  while(P4IN&1);
+  SETRST;//Woken.
+  //debugstr("EM260 is now awake.");
+  delay(1024);  //DO NOT REMOVE, fails without.
+}
+
 //! Handles a monitor command.
 void spihandle(unsigned char app,
               unsigned char verb,
@@ -240,8 +254,40 @@ void spihandle(unsigned char app,
     SETSS;  //Raise !SS to end transaction.
     txdata(app,verb,len);
     break;
-
-
+    
+  case SPI_RW_EM260:  //SPI exchange with an EM260
+    P4DIR=0; //TODO ASAP remove P4 references.
+    P4OUT=0;
+    
+    //See GoodFETEM260.py for details.
+    //The EM260 requires that the host wait for the client.
+    
+    em260_wake();
+    
+    SETMOSI; //Autodetected SPI mode.
+    CLRSS; //Drop !SS to begin transaction.
+    //Host to slave.  Ignore data.
+    for(i=0;i<len;i++)
+      spitrans8(cmddata[i]);
+    //debugstr("Finished transmission to EM260.");
+    
+    //Could also wait for nHOST_INT to drop.
+    i=0xffff;
+    while((cmddata[0]=spitrans8(0xFF))==0xFF
+         && --i);
+    if(!i)
+      debugstr("Gave up on host interrupt.");
+        
+    len=64;
+    for(i=0;i<len;i++)
+      cmddata[i]=spitrans8(0xFF);
+    
+    
+    SETSS;  //Raise !SS to end transaction.
+    txdata(app,verb,len);
+    break;
+    
+    
   case SPI_JEDEC://Grab 3-byte JEDEC ID.
     CLRSS; //Drop !SS to begin transaction.
     spitrans8(0x9f);
@@ -251,8 +297,7 @@ void spihandle(unsigned char app,
     txdata(app,verb,len);
     SETSS;  //Raise !SS to end transaction.
     break;
-
-
+    
   case PEEK://Grab 128 bytes from an SPI Flash ROM
     spiflash_peek(app,verb,len);
     break;

diff --git a/firmware/goodfet.c b/firmware/goodfet.c
index acf6772..b8d9e3d 100644 (file)
--- a/firmware/goodfet.c
+++ b/firmware/goodfet.c
@@ -41,9 +41,14 @@ void init(){
    relates to the FTDI on-chip 3V3 regulator being specified up to
    only 50 mA. */
   
-  P5DIR |= BIT0;
+  
   //P5REN &= ~BIT0; //DO NOT UNCOMMENT.  Breaks GF1x support.
+  
+  //This will have to be cut soon.  Use pulling resistors instead.
+  /*
+  P5DIR |= BIT0;
   P5OUT &= ~BIT0;
+  */
   
   //Setup clocks, unique to each '430.
   msp430_init_dco();

diff --git a/firmware/include/command.h b/firmware/include/command.h
index 5690229..d514e49 100644 (file)
--- a/firmware/include/command.h
+++ b/firmware/include/command.h
@@ -53,6 +53,7 @@ extern unsigned char silent;
 //SPI commands
 #define SPI_JEDEC 0x80
 #define SPI_ERASE 0x81
+#define SPI_RW_EM260 0x82
 
 //OCT commands
 #define OCT_CMP 0x90

diff --git a/firmware/include/spi.h b/firmware/include/spi.h
index 02e548a..590db0e 100644 (file)
--- a/firmware/include/spi.h
+++ b/firmware/include/spi.h
@@ -16,6 +16,12 @@
 #define CLRCLK P5OUT&=~SCK
 #define READMISO (P5IN&MISO?1:0)
 
+#define SETTST P4OUT|=TST
+#define CLRTST P4OUT&=~TST
+#define SETRST P2OUT|=RST
+#define CLRRST P2OUT&=~RST
+
+
 //! Set up the pins for SPI mode.
 void spisetup();
 

diff --git a/firmware/platforms/goodfet.h b/firmware/platforms/goodfet.h
index 9364dbb..ba9b0c2 100644 (file)
--- a/firmware/platforms/goodfet.h
+++ b/firmware/platforms/goodfet.h
@@ -38,3 +38,4 @@
 #define SETCE P5OUT|=BIT5
 #define CLRCE P5OUT&=~BIT5
 #define DIRCE P5DIR|=BIT5
+