+/************************************************************************
+* ARM7TDMI core has 6 primary registers to be connected between TDI/TDO
+* * Bypass Register
+* * ID Code Register
+* * Scan Chain Select Register (4 bits_lsb)
+* * Scan Chain 0 (64+* bits: 32_databits_lsb + ctrlbits + 32_addrbits_msb)
+* * Scan Chain 1 (33 bits: 32_bits + BREAKPT)
+* * Scan Chain 2 (38 bits: rw + 5_regbits_msb + 32_databits_msb)
+************************************************************************/
+
+
+
+/************************** Basic JTAG Verb Commands *******************************/
+//! Grab the core ID.
+unsigned long jtagarm7tdmi_idcode(){ // PROVEN
+ SHIFT_IR;
+ jtagarmtransn(ARM7TDMI_IR_IDCODE, 4, LSB, END, RETIDLE);
+ SHIFT_DR;
+ return jtagarmtransn(0,32, LSB, END, RETIDLE);
+}
+
+//! Connect Bypass Register to TDO/TDI
+unsigned char jtagarm7tdmi_bypass(){ // PROVEN
+ SHIFT_IR;
+ return jtagarmtransn(ARM7TDMI_IR_BYPASS, 4, LSB, END, NORETIDLE);
+}
+//! INTEST verb - do internal test
+unsigned char jtagarm7tdmi_intest() {
+ SHIFT_IR;
+ return jtagarmtransn(ARM7TDMI_IR_INTEST, 4, LSB, END, NORETIDLE);
+}
+
+//! EXTEST verb
+unsigned char jtagarm7tdmi_extest() {
+ SHIFT_IR;
+ return jtagarmtransn(ARM7TDMI_IR_EXTEST, 4, LSB, END, NORETIDLE);
+}
+
+//! SAMPLE verb
+//unsigned long jtagarm7tdmi_sample() {
+// jtagarm7tdmi_ir_shift4(ARM7TDMI_IR_SAMPLE); // ???? same here.
+// return jtagtransn(0,32);
+//}
+
+//! RESTART verb
+unsigned char jtagarm7tdmi_restart() {
+ SHIFT_IR;
+ return jtagarmtransn(ARM7TDMI_IR_RESTART, 4, LSB, END, RETIDLE);
+}
+
+//! ARM7TDMI_IR_CLAMP 0x5
+unsigned long jtagarm7tdmi_clamp() {
+ SHIFT_IR;
+ jtagarmtransn(ARM7TDMI_IR_CLAMP, 4, LSB, END, NORETIDLE);
+ SHIFT_DR;
+ return jtagarmtransn(0, 32, LSB, END, RETIDLE);
+}
+
+//! ARM7TDMI_IR_HIGHZ 0x7
+unsigned char jtagarm7tdmi_highz() {
+ SHIFT_IR;
+ return jtagarmtransn(ARM7TDMI_IR_HIGHZ, 4, LSB, END, NORETIDLE);
+}
+
+//! define ARM7TDMI_IR_CLAMPZ 0x9
+unsigned char jtagarm7tdmi_clampz() {
+ SHIFT_IR;
+ return jtagarmtransn(ARM7TDMI_IR_CLAMPZ, 4, LSB, END, NORETIDLE);
+}
+
+
+//! Connect the appropriate scan chain to TDO/TDI. SCAN_N, INTEST, ENDS IN SHIFT_DR!!!!!
+unsigned long jtagarm7tdmi_scan(int chain, int testmode) { // PROVEN
+/*
+When selecting a scan chain the “Run Test/Idle” state should never be reached, other-
+wise, when in debug state, the core will not be correctly isolated and intrusive
+commands occur. Therefore, it is recommended to pass directly from the “Update”
+state” to the “Select DR” state each time the “Update” state is reached.
+*/
+ jtagarm7tdmi_resettap(); // assume already sane?
+ unsigned long retval;
+ //if (current_chain != chain) { // breaks shit when going from idcode back to scan chain
+ SHIFT_IR;
+ jtagarmtransn(ARM7TDMI_IR_SCAN_N, 4, LSB, END, NORETIDLE);
+ SHIFT_DR;
+ retval = jtagarmtransn(chain, 4, LSB, END, NORETIDLE);
+ current_chain = chain;
+ //} else
+ // retval = current_chain;
+ // put in test mode...
+ SHIFT_IR;
+ jtagarmtransn(testmode, 4, LSB, END, RETIDLE);
+ return(retval);
+}
+
+
+//! Connect the appropriate scan chain to TDO/TDI. SCAN_N, INTEST, ENDS IN SHIFT_DR!!!!!
+unsigned long jtagarm7tdmi_scan_intest(int chain) { // PROVEN
+ return jtagarm7tdmi_scan(chain, ARM7TDMI_IR_INTEST);
+}
+
+/* unsigned long retval;
+ if (current_chain == chain)
+ return current_chain;
+ jtagarm7tdmi_resettap(); // assumed already sane?
+ SHIFT_IR;
+ jtagarmtransn(ARM7TDMI_IR_SCAN_N, 4, LSB, END, NORETIDLE);
+ SHIFT_DR;
+ retval = jtagarmtransn(chain, 4, LSB, END, NORETIDLE);
+ current_chain = chain;
+ jtagarm7tdmi_intest();
+ //SHIFT_DR;
+ return(retval);
+}
+*/
+
+
+
projects / goodfet / commitdiff