Writing of SPI Flash works just after it is plugged in,

but fails afterward.  A curious bug.

git-svn-id: https://svn.code.sf.net/p/goodfet/code/trunk@68 12e2690d-a6be-4b82-a7b7-67c4a43b65c8

diff --git a/client/GoodFET.py b/client/GoodFET.py
index f2a673b..cbcf1c4 100755 (executable)
--- a/client/GoodFET.py
+++ b/client/GoodFET.py
@@ -153,20 +153,21 @@ class GoodFET:
         
         self.writecmd(0x01,0x02,3,data);
         return self.data;
         
         self.writecmd(0x01,0x02,3,data);
         return self.data;

+    

     def SPIpokebyte(self,adr,val):
     def SPIpokebyte(self,adr,val):

-        self.SPIwriteenable();
-        data=[0x02,
-              (adr&0xFF0000)>>16,
+        self.SPIpokebytes(adr,[val]);
+    def SPIpokebytes(self,adr,data):
+        #self.SPIwriteenable();
+        adranddata=[(adr&0xFF0000)>>16,

               (adr&0xFF00)>>8,
               (adr&0xFF00)>>8,

-              adr&0xFF,
-              val];
-        self.SPItrans(data);
+              adr&0xFF
+              ]+data;
+        self.writecmd(0x01,0x03,
+                      len(adranddata),adranddata);
+        

     def SPIchiperase(self):
         """Mass erase an SPI Flash ROM."""
     def SPIchiperase(self):
         """Mass erase an SPI Flash ROM."""

-        self.SPIwriteenable();
-        #Chip Erase
-        data=[0xC7];
-        self.SPItrans(data);
+        self.writecmd(0x01,0x81,0,[]);

     def SPIwriteenable(self):
         """SPI Flash Write Enable"""
         data=[0x06];
     def SPIwriteenable(self):
         """SPI Flash Write Enable"""
         data=[0x06];

diff --git a/firmware/apps/spi/spi.c b/firmware/apps/spi/spi.c
index 0a15799..c58b4bc 100644 (file)
--- a/firmware/apps/spi/spi.c
+++ b/firmware/apps/spi/spi.c
@@ -68,12 +68,30 @@ unsigned char spitrans8(unsigned char byte){
 
 //! Enable SPI writing
 void spiflash_wrten(){
 
 //! Enable SPI writing
 void spiflash_wrten(){

-    P5OUT&=~SS; //Drop !SS to begin transaction.
-    spitrans8(0x04);//Write Disable
-    P5OUT|=SS;  //Raise !SS to end transaction.
-    P5OUT&=~SS; //Drop !SS to begin transaction.
-    spitrans8(0x06);//Write Enable
-    P5OUT|=SS;  //Raise !SS to end transaction.
+  P5OUT&=~SS; //Drop !SS to begin transaction.
+  spitrans8(0x04);//Write Disable
+  P5OUT|=SS;  //Raise !SS to end transaction.
+  P5OUT&=~SS; //Drop !SS to begin transaction.
+  spitrans8(0x06);//Write Enable
+  P5OUT|=SS;  //Raise !SS to end transaction.
+}
+
+//! Grab the SPI flash status byte.
+unsigned char spiflash_status(){
+  unsigned char c;
+  P5OUT&=~SS; //Drop !SS to begin transaction.
+  spitrans8(0x05);//GET STATUS
+  c=spitrans8(0xFF);
+  P5OUT|=SS;  //Raise !SS to end transaction.
+  return c;
+}
+//! Grab the SPI flash status byte.
+void spiflash_setstatus(unsigned char c){
+  P5OUT&=~SS; //Drop !SS to begin transaction.
+  spitrans8(0x01);//SET STATUS
+  spitrans8(c);
+  P5OUT|=SS;  //Raise !SS to end transaction.
+  return c;

 }
 
 //! Handles a monitor command.
 }
 
 //! Handles a monitor command.


@@ -113,7 +131,9 @@ void spihandle(unsigned char app,
     P5OUT|=SS;  //Raise !SS to end transaction.
     break;
   case POKE://Poke up bytes from an SPI Flash ROM.
     P5OUT|=SS;  //Raise !SS to end transaction.
     break;
   case POKE://Poke up bytes from an SPI Flash ROM.

+    spiflash_setstatus(0x02);

     spiflash_wrten();
     spiflash_wrten();

+    

     P5OUT&=~SS; //Drop !SS to begin transaction.
     spitrans8(0x02); //Poke command.
     
     P5OUT&=~SS; //Drop !SS to begin transaction.
     spitrans8(0x02); //Poke command.
     


@@ -121,6 +141,8 @@ void spihandle(unsigned char app,
     for(i=0;i<len;i++)
       spitrans8(cmddata[i]);
     P5OUT&=~SS; //Drop !SS to begin transaction.
     for(i=0;i<len;i++)
       spitrans8(cmddata[i]);
     P5OUT&=~SS; //Drop !SS to begin transaction.

+    while(spiflash_status()&0x01);//while busy
+    spiflash_wrten();

     txdata(app,verb,len);
     break;
   case SPI_ERASE://Erase the SPI Flash ROM.
     txdata(app,verb,len);
     break;
   case SPI_ERASE://Erase the SPI Flash ROM.