+# These targets are compiled to execute at the beginning of RAM.
+# Each should conclude with HALT (0xA5).
CC=sdcc --code-loc 0xF000
objs=crystal.ihx
CC=sdcc --code-loc 0xF000
objs=crystal.ihx
#define _IOCCXX10_BITDEF_H\r
\r
\r
#define _IOCCXX10_BITDEF_H\r
\r
\r
+//Added by Travis Goodspeed\r
+#define HALT __asm \\r
+ .byte 0xA5 \\r
+ __endasm;\r
+\r
\r
/* SEE DATA SHEET FOR DETAILS ABOUT THE FOLLOWING BIT MASKS */\r
\r
\r
/* SEE DATA SHEET FOR DETAILS ABOUT THE FOLLOWING BIT MASKS */\r
\r
CLKCON = (CLKCON & ~(CLKCON_CLKSPD | CLKCON_OSC)) | CLKSPD_DIV_1; // Select xtal osc, 26 MHz
while (CLKCON & CLKCON_OSC); // Wait for change to take effect
SLEEP |= SLEEP_OSC_PD; // Turn off the other high speed oscillator (the RC osc)
CLKCON = (CLKCON & ~(CLKCON_CLKSPD | CLKCON_OSC)) | CLKSPD_DIV_1; // Select xtal osc, 26 MHz
while (CLKCON & CLKCON_OSC); // Wait for change to take effect
SLEEP |= SLEEP_OSC_PD; // Turn off the other high speed oscillator (the RC osc)