updates.

git-svn-id: https://svn.code.sf.net/p/goodfet/code/trunk@687 12e2690d-a6be-4b82-a7b7-67c4a43b65c8

diff --git a/firmware/apps/i2c/i2c.c b/firmware/apps/i2c/i2c.c
index dc26032..c107397 100644 (file)
--- a/firmware/apps/i2c/i2c.c
+++ b/firmware/apps/i2c/i2c.c
@@ -51,7 +51,7 @@ void I2C_Init()
   //(Pull-up or 0.)
   
   P5DIR|=(SDA|SCL);
-  P5REN|=SDA|SCL;
+  //P5REN|=SDA|SCL;
   
   
   I2C_CLOCK_HI();

diff --git a/firmware/apps/jtag/jtagarm7tdmi.c b/firmware/apps/jtag/jtagarm7tdmi.c
index 541d688..96ea2cd 100644 (file)
--- a/firmware/apps/jtag/jtagarm7tdmi.c
+++ b/firmware/apps/jtag/jtagarm7tdmi.c
@@ -307,19 +307,23 @@ commands occur. Therefore, it is recommended to pass directly from the “Update
 state” to the “Select DR” state each time the “Update” state is reached.
 */
   unsigned long retval;
-  if (current_chain != chain) {
-    debugstr("===change chains===");
+  //if (current_chain != chain) {
+  //  //debugstr("===change chains===");
     jtag_goto_shift_ir();
     jtagarmtransn(ARM7TDMI_IR_SCAN_N, 4, LSB, END, NORETIDLE);
     jtag_goto_shift_dr();
     retval = jtagarmtransn(chain, 4, LSB, END, NORETIDLE);
     // put in test mode...
-    jtag_goto_shift_ir();
-    jtagarmtransn(testmode, 4, LSB, END, RETIDLE); 
+    //jtag_goto_shift_ir();
+    //jtagarmtransn(testmode, 4, LSB, END, RETIDLE); 
     current_chain = chain;
-  }    else
-    debugstr("===NOT change chains===");
-    retval = current_chain;
+  //}    else  {
+  //  //debugstr("===NOT change chains===");
+  //  retval = current_chain;
+  //}
+  // put in test mode...
+  jtag_goto_shift_ir();
+  jtagarmtransn(testmode, 4, LSB, END, RETIDLE); 
   return(retval);
 }
 
@@ -991,6 +995,19 @@ void jtagarm7tdmihandle(unsigned char app, unsigned char verb, unsigned long len
     cmddatalong[0] = jtagarmtransn(cmddatalong[1],cmddata[0],cmddata[1],cmddata[2],cmddata[3]);
     txdata(app,verb,4);
     break;
+  case JTAGARM7TDMI_CHAIN0:
+    jtagarm7tdmi_scan_intest(0);
+    jtag_goto_shift_dr();
+    debughex32(cmddatalong[0]);
+    debughex(cmddataword[4]);
+    debughex32(cmddatalong[1]);
+    debughex32(cmddatalong[3]);
+    cmddatalong[0] = jtagarmtransn(cmddatalong[0], 32, LSB, NOEND, NORETIDLE);
+    cmddatalong[2] = jtagarmtransn(cmddataword[4], 9, MSB, NOEND, NORETIDLE);
+    cmddatalong[1] = jtagarmtransn(cmddatalong[1], 32, MSB, NOEND, NORETIDLE);
+    cmddatalong[3] = jtagarmtransn(cmddatalong[3], 32, MSB, END, RETIDLE);
+    txdata(app,verb,16);
+    break;
   case JTAGARM7TDMI_SETWATCH0:
     jtagarm7tdmi_set_watchpoint0(cmddatalong[0], cmddatalong[1], cmddatalong[2], cmddatalong[3], cmddatalong[4], cmddatalong[5]);
     txdata(app,verb,4);

diff --git a/firmware/include/jtagarm7tdmi.h b/firmware/include/jtagarm7tdmi.h
index 770f8c1..3e2045d 100644 (file)
--- a/firmware/include/jtagarm7tdmi.h
+++ b/firmware/include/jtagarm7tdmi.h
@@ -175,6 +175,7 @@ The least significant bit of the instruction register is scanned in and scanned
 #define JTAGARM7TDMI_SHIFT_DR             0xa0
 #define JTAGARM7TDMI_SETWATCH0            0xa1
 #define JTAGARM7TDMI_SETWATCH1            0xa2
+#define JTAGARM7TDMI_CHAIN0               0xa3
 
 
 // for deeper understanding, read the instruction cycle timing section of: