Adding preliminary support for the MSP430F2618, build with CVS MSPGCC as
authortravisutk <travisutk@12e2690d-a6be-4b82-a7b7-67c4a43b65c8>
Sun, 23 Aug 2009 12:19:39 +0000 (12:19 +0000)
committertravisutk <travisutk@12e2690d-a6be-4b82-a7b7-67c4a43b65c8>
Sun, 23 Aug 2009 12:19:39 +0000 (12:19 +0000)
mcu=msp430x2618 make -e

git-svn-id: https://svn.code.sf.net/p/goodfet/code/trunk@84 12e2690d-a6be-4b82-a7b7-67c4a43b65c8

firmware/README.txt
firmware/lib/msp430x1612.c
firmware/lib/msp430x2618.c [new file with mode: 0644]

index cc85ad7..6e7cc44 100644 (file)
@@ -4,6 +4,10 @@ by Travis Goodspeed
 
 Requires MSPGCC and msp430-bsl.
 
-Assumes MSP430F161x by default.  Call for others by
-mcu=msp430x2618 make -e
+Assumes MSP430F161x by default.  Call for others by the following method,
+recognizing that 2618 support is a rather recent addition and only works
+in MSPGCC from CVS.
+
+export mcu=msp430x2618
+make -e
 
index e1d03a7..3bcb3ce 100644 (file)
@@ -74,122 +74,29 @@ void setbaud1(unsigned char rate){
   //http://mspgcc.sourceforge.net/baudrate.html
   switch(rate){
   case 1://9600 baud
-    UBR01=0x7F; UBR11=0x01; UMCTL1=0x5B; /* uart0 3683400Hz 9599bps */
+    //    UBR01=0x7F; UBR11=0x01; UMCTL1=0x5B; /* uart0 3683400Hz 9599bps */
     break;
   case 2://19200 baud
-    UBR01=0xBF; UBR11=0x00; UMCTL1=0xF7; /* uart0 3683400Hz 19194bps */
+    //UBR01=0xBF; UBR11=0x00; UMCTL1=0xF7; /* uart0 3683400Hz 19194bps */
     break;
   case 3://38400 baud
-    UBR01=0x5F; UBR11=0x00; UMCTL1=0xBF; /* uart0 3683400Hz 38408bps */
+    //UBR01=0x5F; UBR11=0x00; UMCTL1=0xBF; /* uart0 3683400Hz 38408bps */
     break;
   case 4://57600 baud
-    UBR01=0x40; UBR11=0x00; UMCTL1=0x00; /* uart0 3683400Hz 57553bps */
+    //UBR01=0x40; UBR11=0x00; UMCTL1=0x00; /* uart0 3683400Hz 57553bps */
     break;
   default:
   case 5://115200 baud
-    UBR01=0x20; UBR11=0x00; UMCTL1=0x00; /* uart0 3683400Hz 115106bps */
+    //UBR01=0x20; UBR11=0x00; UMCTL1=0x00; /* uart0 3683400Hz 115106bps */
     break;
   }
 }
 
 
 void msp430_init_uart(){
-  
-  P3SEL |= BIT4|BIT5;                        // P3.4,5 = USART0 TXD/RXD
-  P3DIR |= BIT4;
-  
-  UCTL0 = SWRST | CHAR;                 /* 8-bit character, UART mode */
-  UTCTL0 = SSEL1;                       /* UCLK = MCLK */
-  
-  setbaud(0);
-  
-  //Necessary for bit-banging, switch to hardware for performance.
-  ME1 &= ~USPIE0;                      /* USART1 SPI module disable */
-  ME1 |= (UTXE0 | URXE0);               /* Enable USART1 TXD/RXD */
-
-  UCTL0 &= ~SWRST;
-
-  /* XXX Clear pending interrupts before enable!!! */
-  U0TCTL |= URXSE;
-  
-  
-  //IE1 |= URXIE1;                        /* Enable USART1 RX interrupt  */
 }
 
 
 void msp430_init_dco() {
-    /* This code taken from the FU Berlin sources and reformatted. */
-  //
-
-//Works well.
-//#define MSP430_CPU_SPEED 2457600UL
-
-//Too fast for internal resistor.
-//#define MSP430_CPU_SPEED 4915200UL
-
-//Max speed.
-//#deefine MSP430_CPU_SPEED 4500000UL
-
-//baud rate speed
-#define MSP430_CPU_SPEED 3683400UL
-#define DELTA    ((MSP430_CPU_SPEED) / (32768 / 8))
-  unsigned int compare, oldcapture = 0;
-  unsigned int i;
-  
-  WDTCTL = WDTPW + WDTHOLD; //stop WDT
-  
-  
-  DCOCTL=0xF0;
-  //a4
-  //1100
-
-  /* ACLK is devided by 4. RSEL=6 no division for MCLK
-     and SSMCLK. XT2 is off. */
-  //BCSCTL1 = 0xa8;
-  
-  BCSCTL2 = 0x00; /* Init FLL to desired frequency using the 32762Hz
-                    crystal DCO frquenzy = 2,4576 MHz  */
-  
-  P1OUT|=1;
-  
-  BCSCTL1 |= DIVA1 + DIVA0;             /* ACLK = LFXT1CLK/8 */
-  for(i = 0xffff; i > 0; i--) {         /* Delay for XTAL to settle */
-    asm("nop");
-  }
-
-  CCTL2 = CCIS0 + CM0 + CAP;            // Define CCR2, CAP, ACLK
-  TACTL = TASSEL1 + TACLR + MC1;        // SMCLK, continous mode
-
-
-  while(1) {
-
-    while((CCTL2 & CCIFG) != CCIFG);    /* Wait until capture occured! */
-    CCTL2 &= ~CCIFG;                    /* Capture occured, clear flag */
-    compare = CCR2;                     /* Get current captured SMCLK */
-    compare = compare - oldcapture;     /* SMCLK difference */
-    oldcapture = CCR2;                  /* Save current captured SMCLK */
-
-    if(DELTA == compare) {
-      break;                            /* if equal, leave "while(1)" */
-    } else if(DELTA < compare) {        /* DCO is too fast, slow it down */
-      DCOCTL--;
-      if(DCOCTL == 0xFF) {              /* Did DCO role under? */
-       BCSCTL1--;
-      }
-    } else {                            /* -> Select next lower RSEL */
-      DCOCTL++;
-      if(DCOCTL == 0x00) {              /* Did DCO role over? */
-       BCSCTL1++;
-      }
-                                        /* -> Select next higher RSEL  */
-    }
-  }
-  
-  CCTL2 = 0;                            /* Stop CCR2 function */
-  TACTL = 0;                            /* Stop Timer_A */
-
-  BCSCTL1 &= ~(DIVA1 + DIVA0);          /* remove /8 divisor from ACLK again */
-  
-  P1OUT=0;
 }
 
diff --git a/firmware/lib/msp430x2618.c b/firmware/lib/msp430x2618.c
new file mode 100644 (file)
index 0000000..02ee1c0
--- /dev/null
@@ -0,0 +1,123 @@
+//! MSP430F2618 clock and I/O definitions
+
+// Ought to be portable to other 2xx chips.
+// 2274 looks particularly appealing.
+
+#include "platform.h"
+
+#include <signal.h>
+#include <io.h>
+#include <iomacros.h>
+
+
+//! Receive a byte.
+unsigned char serial_rx(){
+  char c;
+  
+  while(!(IFG2&UCA0RXIFG));//wait for a byte
+  c = UCA0RXBUF;
+  IFG2&=~UCA0RXIFG;
+  
+  //UCA0CTL1 &= ~UCA0RXSE;
+  return c;
+}
+
+//! Receive a byte.
+unsigned char serial1_rx(){
+  //TODO
+}
+
+
+//! Transmit a byte.
+void serial_tx(unsigned char x){
+  while ((IFG2 & UCA0TXIFG) == 0); //loop unti lbuffer is free
+  UCA0TXBUF = x;       /* send the character */
+  while(!(IFG2 & UCA0TXIFG));
+}
+
+//! Transmit a byte on the second UART.
+void serial1_tx(unsigned char x){
+}
+
+//! Set the baud rate.
+void setbaud(unsigned char rate){
+  
+  //http://mspgcc.sourceforge.net/baudrate.html
+  switch(rate){
+  case 1://9600 baud
+    
+    break;
+  case 2://19200 baud
+    
+    break;
+  case 3://38400 baud
+    
+    break;
+  case 4://57600 baud
+    
+    break;
+  default:
+  case 5://115200 baud
+    
+    break;
+  }
+}
+
+//! Set the baud rate of the second uart.
+void setbaud1(unsigned char rate){
+  
+  //http://mspgcc.sourceforge.net/baudrate.html
+  switch(rate){
+  case 1://9600 baud
+    
+    break;
+  case 2://19200 baud
+    
+    break;
+  case 3://38400 baud
+    
+    break;
+  case 4://57600 baud
+    
+    break;
+  default:
+  case 5://115200 baud
+    
+    break;
+  }
+}
+
+
+//host.h says 0x2B for DCO=4.9MHZ
+//Divide by four for accuracy.
+
+//19200
+#define BAUD0EN 0x41
+#define BAUD1EN 0x03
+
+
+void msp430_init_uart(){
+  // Serial on P3.4, P3.5
+  P3SEL |= BIT4 + BIT5;
+  P3DIR |= BIT4;
+  
+  //UCA0CTL1 |= UCSWRST;                    /* disable UART */
+
+  UCA0CTL0 = 0x00;
+  //UCA0CTL0 |= UCMSB ;
+  UCA0CTL1 |= UCSSEL_2;                     // SMCLK
+  UCA0BR0 = BAUD0EN;                        // 115200
+  UCA0BR1 = BAUD1EN;
+  UCA0MCTL = 0;                             // Modulation UCBRSx = 5
+  UCA0CTL1 &= ~UCSWRST;                     // **Initialize USCI state machine**
+  
+}
+
+
+void msp430_init_dco() {
+  BCSCTL1 = CALBC1_16MHZ;
+  DCOCTL = CALDCO_16MHZ;
+  
+  return;
+}
+