//Port output BUT NOT DIRECTION is set at start.
P5OUT|=MOSI+SCK+RST;
- delay(30); //So the beginning is ready for glitching.
+ //delay(30); //So the beginning is ready for glitching.
//Two positive debug clock pulses while !RST is low.
//Take RST low, pulse twice, then high.
txdata(app,verb,0);
break;
case START://enter debugger
- //ccsetup(); //interferes with glitching
ccdebuginit();
txdata(app,verb,0);
break;
WDTCTL = WDTPW + WDTHOLD; // Stop WDT
TACTL = TASSEL1 + TACLR; // SMCLK, clear TAR
CCTL0 = CCIE; // CCR0 interrupt enabled
- CCR0 = glitchcount+0x15; //clock divider
- TACTL |= MC_3;
+ CCR0 = glitchcount+0x15; // Compare Value
+ TACTL |= MC_2; // continuous mode.
#endif
}
TACTL=0; //clear dividers
TACTL|=TACLR; //clear config
TACTL|=TASSEL_SMCLK| //smclk source
- MC_2; //continuout mode.
+ MC_2; //continuous mode.
//perform the function
silent++;//Don't want the function to return anything.
txdata(app,verb,2);
break;
case START:
+ //Testing mode, for looking at the glitch waveform.
glitchvoltages(0xFFF,0);//Inverted VCC and GND.
P5OUT|=BIT7;//Normal
P5DIR|=BIT7;