updates to ADIv5, ARM7, AT91x40, and the flash modules M29W640GB. good stuff.

git-svn-id: https://svn.code.sf.net/p/goodfet/code/trunk@759 12e2690d-a6be-4b82-a7b7-67c4a43b65c8

diff --git a/client/GoodFETADIv5.py b/client/GoodFETADIv5.py
index e4f1f91..bfcad94 100644 (file)
--- a/client/GoodFETADIv5.py
+++ b/client/GoodFETADIv5.py
@@ -407,65 +407,70 @@ class ADI_MEM_AP(ADI_AccessPort):
         # FIXME: how do i determine if this adi supports multibyte access or just word?  or packed transfers?
         self.setMemAccessSize(4)
 
-    def setMemAccessSize(self, bytecount):
-        csw = self.getCSW()
-        csw &= 0xfffffff8
-        csw |= (bytecount>>1)
-        self.setCSW(csw)
-
     def getCSW(self):
-        return self.getRegister(MEMAP_CSW_REG)
+        """ Control/Status Word reg  """
+        return self.getRegister(self.MEMAP_CSW_REG)
     def setCSW(self, csw):
-        return self.setRegister(MEMAP_CSW_REG, csw)
+        """ Control/Status Word reg.  Some bits are RO """
+        return self.setRegister(self.MEMAP_CSW_REG, csw)
+    def reprCSW(self):
+        csw = self.getCSW()
+        
 
     def getTAR(self):
-        return self.getRegister(MEMAP_TAR_REG)
+        """ Transfer Address Register.  Used for both DRW and BDx accesses.  Autoinc (see CSW) only works for DRW accesses, not Banked Regs"""
+        return self.getRegister(self.MEMAP_TAR_REG)
     def setTAR(self, tar):
-        return self.setRegister(MEMAP_TAR_REG, tar)
+        """ Transfer Address Register.  Used for both DRW and BDx accesses.  Autoinc (see CSW) only works for DRW accesses, not Banked Regs"""
+        return self.setRegister(self.MEMAP_TAR_REG, tar)
 
     def getDRW(self):
-        return self.getRegister(MEMAP_DRW_REG)
+        """ Data Read/Write reg. """
+        return self.getRegister(self.MEMAP_DRW_REG)
     def setDRW(self, drw):
-        return self.setRegister(MEMAP_DRW_REG, drw)
+        """ Data Read/Write reg. """
+        return self.setRegister(self.MEMAP_DRW_REG, drw)
 
     #FIXME: use one set of accessors... either keep the indexed version or the individuals.
-    def getBankedReg(self, index):
-        return self.getRegister(MEMAP_BD0_REG + (index*4))
-    def setBankedReg(self, index, bd):
-        return self.setRegister(MEMAP_BD0_REG + (index*4), bd0)
+    def getBDReg(self, index):
+        return self.getRegister(self.MEMAP_BD0_REG + (index*4))
+    def setBDReg(self, index, bd):
+        return self.setRegister(self.MEMAP_BD0_REG + (index*4), bd0)
 
     def getBD0(self):
-        return self.getRegister(MEMAP_BD0_REG)
+        return self.getRegister(self.MEMAP_BD0_REG)
     def setBD0(self, bd0):
-        return self.setRegister(MEMAP_BD0_REG, bd0)
+        return self.setRegister(self.MEMAP_BD0_REG, bd0)
 
     def getBD1(self):
-        return self.getRegister(MEMAP_BD1_REG)
+        return self.getRegister(self.MEMAP_BD1_REG)
     def setBD1(self, bd1):
-        return self.setRegister(MEMAP_BD1_REG, bd1)
+        return self.setRegister(self.MEMAP_BD1_REG, bd1)
 
     def getBD2(self):
-        return self.getRegister(MEMAP_BD2_REG)
+        return self.getRegister(self.MEMAP_BD2_REG)
     def setBD2(self, bd2):
-        return self.setRegister(MEMAP_BD2_REG, bd2)
+        return self.setRegister(self.MEMAP_BD2_REG, bd2)
 
     def getBD3(self):
-        return self.getRegister(MEMAP_BD3_REG)
+        return self.getRegister(self.MEMAP_BD3_REG)
     def setBD3(self, bd3):
-        return self.setRegister(MEMAP_BD3_REG, bd3)
+        return self.setRegister(self.MEMAP_BD3_REG, bd3)
 
     def getCFG(self):
-        return self.getRegister(MEMAP_CFG_REG)
+        return self.getRegister(self.MEMAP_CFG_REG)
     def setCFG(self, cfg):
-        return self.setRegister(MEMAP_CFG_REG, cfg)
+        return self.setRegister(self.MEMAP_CFG_REG, cfg)
 
     def getBASE(self):
-        return self.getRegister(MEMAP_BASE_REG)
+        """ BASE debug address.  RO """
+        return self.getRegister(self.MEMAP_BASE_REG)
     def setBASE(self, base):
-        return self.setRegister(MEMAP_BASE_REG, base)
+        """ BASE debug address.  RO """
+        return self.setRegister(self.MEMAP_BASE_REG, base)
 
     def getIDR(self):
-        return self.getRegister(MEMAP_IDR_REG)
+        return self.getRegister(self.MEMAP_IDR_REG)
 
     # CFG accessors
     CFG_DBGSWENABLE_BITS =      31
@@ -484,10 +489,27 @@ class ADI_MEM_AP(ADI_AccessPort):
     CFG_ADDRINC =               3<<4
     CFG_SIZE_BITS =             0
     CFG_SIZE =                  7
-    def CFG_setDbgSwEnable(self, bit):
-        cfg = self.getCFG() & CFG_DBGSWENABLE
-        cfg |= (bit<<CFG_DBGSWENABLE_BITS)
-    def CFG_getDbgSwEnable(self):
-        cfg = (self.getCFG() & CFG_DBGSWENABLE) >> CFG_DBGSWENABLE_BITS
+    CFG_ADDRINC_off =           0b00
+    CFG_ADDRINC_single =        0b01
+    CFG_ADDRINC_packed =        0b10
+    CFG_MEM_8bits =             0b000
+    CFG_MEM_16bits =            0b001
+    CFG_MEM_32bits =            0b010
+    def CSWsetDbgSwEnable(self, bit):
+        cfg = self.getCFG() & self.CFG_DBGSWENABLE
+        cfg |= (bit<<self.CFG_DBGSWENABLE_BITS)
+    def CSWgetDbgSwEnable(self):
+        cfg = (self.getCFG() & self.CFG_DBGSWENABLE) >> self.CFG_DBGSWENABLE_BITS
+        return cfg
+
+    def CSWsetAddrInc(self, bits=CFG_ADDRINC_single):
+        cfg = (self.getCFG() & self.CFG_ADDRINC) >> self.CFG_ADDRINC_BITS
+        cfg |= (bit<<self.CFG_DBGSWENABLE_BITS)
+    def CSWsetMemAccessSize(self, bytecount=self.CSW_MEM_32bits):        # 0b010 == 32bit words, necessary if the implementation allows for variable sizes
+        csw = self.getCSW()
+        csw &= 0xfffffff8
+        csw |= (bytecount>>1)
+        self.setCSW(csw)
+
 
 

diff --git a/client/GoodFETARM7.py b/client/GoodFETARM7.py
index 0864cb2..206c820 100644 (file)
--- a/client/GoodFETARM7.py
+++ b/client/GoodFETARM7.py
@@ -122,6 +122,8 @@ ARM_INSTR_LDR_R1_r0_4 =     0xe4901004L
 ARM_READ_MEM =              ARM_INSTR_LDR_R1_r0_4
 ARM_INSTR_STR_R1_r0_4 =     0xe4801004L
 ARM_WRITE_MEM =             ARM_INSTR_STR_R1_r0_4
+ARM_INSTR_STRB_R1_r0_1 =    0xe4c01001L
+ARM_WRITE_MEM_BYTE =        ARM_INSTR_STRB_R1_r0_1
 ARM_INSTR_MRS_R0_CPSR =     0xe10f0000L
 ARM_INSTR_MSR_cpsr_cxsf_R0 =0xe12ff000L
 ARM_INSTR_STMIA_R14_r0_rx = 0xE88e0000L      # add up to 65k to indicate which registers...
@@ -542,7 +544,7 @@ class GoodFETARM(GoodFET):
             adr += count*4
             #print hex(adr)
         # FIXME: handle the rest of the wordcount here.
-    def ARMwriteMem(self, adr, wordarray):
+    def ARMwriteMem(self, adr, wordarray, instr=ARM_WRITE_MEM):
         r0 = self.ARMget_register(0);        # store R0 and R1
         r1 = self.ARMget_register(1);
         #print >>sys.stderr,("CPSR:\t%x"%self.ARMget_regCPSR())
@@ -553,13 +555,16 @@ class GoodFETARM(GoodFET):
             self.ARMset_register(1, word);        # write address into R0
             self.ARM_nop(0)
             self.ARM_nop(1)
-            self.ARMdebuginstr(ARM_WRITE_MEM, 0); # push STR R1, [R0], #4 into instruction pipeline  (autoincrements for consecutive writes)
+            self.ARMdebuginstr(instr, 0); # push STR R1, [R0], #4 into instruction pipeline  (autoincrements for consecutive writes)
             self.ARM_nop(0)
             self.ARMrestart()
             self.ARMwaitDBG()
             print >>sys.stderr,hex(self.ARMget_register(1))
         self.ARMset_register(1, r1);       # restore R0 and R1 
         self.ARMset_register(0, r0);
+    def writeMemByte(self, adr, byte):
+        self.ARMwriteMem(adr, byte, ARM_WRITE_MEM_BYTE)
+
 
     ARMstatusbits={
                   0x10 : "TBIT",

diff --git a/client/GoodFETAT91X40.py b/client/GoodFETAT91X40.py
index c7b92e2..cb9c7a8 100644 (file)
--- a/client/GoodFETAT91X40.py
+++ b/client/GoodFETAT91X40.py
@@ -249,7 +249,7 @@ mcr_ale = {
         }
 
 def mcr_decode(mcr):
-    validAddrBits,maxAddrSpace,validCS,codeLabel = mcr_decode[mcr&7]
+    validAddrBits,maxAddrSpace,validCS,codeLabel = mcr_ale[mcr&7]
     drp = mcr>>4
     output = ["Valid Address Bits: %s"%validAddrBits,
             "Maximum Address Space: %xMB"%maxAddrSpace,
@@ -299,7 +299,7 @@ class GoodFETAT91X40(GoodFETARM):
     def setRemap(self):
         self.ARMwriteChunk(EBI_BASE + EBI_OFF_RCR,[REMAP_CMD])
     def getMemoryControlRegister(self):
-        mcr = self.ARMreadMem(EBI_MCR)
+        mcr, = self.ARMreadMem(EBI_MCR)
         return mcr
     def getMemoryControlRegisterstr(self):
         return mcr_decode(self.getMemoryControlRegister())

diff --git a/client/M29W640GB.py b/client/M29W640GB.py
index 3eb5960..e49a255 100644 (file)
--- a/client/M29W640GB.py
+++ b/client/M29W640GB.py
@@ -14,7 +14,7 @@ the 4 Gbytes of address space.
 """
 
 class M29W640G:
-    def __init__(self, addrE, pinE, addrG, pinG, addrW, pinW, chipnum, chip_base_addr=0x1000000):
+    """def __init__(self, addrE, pinE, addrG, pinG, addrW, pinW, chipnum, chip_base_addr=0x1000000):
         self.addrE = addrE
         self.pinE = pinE
         self.addrG = addrG
@@ -23,4 +23,17 @@ class M29W640G:
         self.pinW pinW
         self.chipnum = chipnum
         self.base_addr = chip_base_addr
+        """
+    def __init__(self, gfclient, chipnum, chip_base_addr=0x10000000):
+        self.gfclient = gfclient
+        self.chipnum = chipnum
+        self.base_addr = chip_base_addr
 
+    def ChipErase(self, rusure=False):
+        if rusure:
+            self.gfclient.writeMemByte(self.base_addr + 0x555, [0xaa])
+            self.gfclient.writeMemByte(self.base_addr + 0x2aa, [0x55])
+            self.gfclient.writeMemByte(self.base_addr + 0x555, [0x80])
+            self.gfclient.writeMemByte(self.base_addr + 0x555, [0xaa])
+            self.gfclient.writeMemByte(self.base_addr + 0x2aa, [0x55])
+            self.gfclient.writeMemByte(self.base_addr + 0x555, [0x10])