From: thequux Date: Wed, 9 Nov 2011 01:41:31 +0000 (+0000) Subject: Added support for uniarch mspgcc4 X-Git-Url: http://git.rot13.org/?p=goodfet;a=commitdiff_plain;h=350c674c6bcd97ec2f883b07e0cf49eb8a480183 Added support for uniarch mspgcc4 git-svn-id: https://svn.code.sf.net/p/goodfet/code/trunk@1057 12e2690d-a6be-4b82-a7b7-67c4a43b65c8 --- diff --git a/firmware/Makefile b/firmware/Makefile index 124e36f..849c5fe 100644 --- a/firmware/Makefile +++ b/firmware/Makefile @@ -9,7 +9,7 @@ #platform?=tilaunchpad platform?=goodfet -# donb +# donb ifeq ($(platform),donbfet) GCC?=avr-gcc mcu?=atmega644p @@ -44,16 +44,20 @@ mcu?=RUNCONFIG GCCINC?= #GCC?=avr-gcc -GCC?=msp430-gcc -T ldscripts/$(mcu).x +# We use -Wl,-dT because gcc adds the msp430mcu definitions at the +# very end of the command line, so they only have an effect for a +# default linker script +GCC?=msp430-gcc +LDFLAGS?=-Wl,-dT ldscripts/msp430.x -CCEXTRA?= $(CFLAGS) -D$(mcu) -D$(platform) -Dplatform=$(platform) -DGCC $(GCCINC) -I include -I platforms +CCEXTRA?= $(CFLAGS) -D$(mcu) -D$(platform) -Dplatform=$(platform) $(GCCINC) -I include -I platforms CC=$(GCC) -Wall -Os -fno-strict-aliasing -g -mmcu=$(mcu) $(CCEXTRA) # Available Applications # ====================== # Below is a list of available applications and their descriptions. -# PRODUCTION: +# PRODUCTION: # None have made it to production grade quality # BETA: @@ -125,17 +129,17 @@ else config ?= monitor chipcon spi jtag430 jtag430x2 avr openocd ccspi endif -# donb +# donb ifeq ($(platform),donbfet) config=monitor avr spi jscan endif # Build the needed list of app and lib object files from the config -apps= +apps= ifeq ($(platform),tilaunchpad) libs= lib/$(platform).o lib/command.o lib/apps.o lib/msp430_serial.o -#libs+=lib/setjmp.o +#libs+=lib/setjmp.o else libs= lib/$(mcu).o lib/command.o lib/dco_calib.o lib/apps.o lib/msp430.o lib/arduino.o endif @@ -377,7 +381,7 @@ erase: $(JTAG) -e $(app).hex else install: $(app).hex - $(MSP430BSL) -e -p $(app).hex + $(MSP430BSL) -e -p $(app).hex installinfo: $(MSP430BSL) -P $(app).hex -p info.txt || true #MSP430F2xx targets only, inelegant. verify: @@ -386,7 +390,7 @@ endif dumpinfo: $(MSP430BSL) --dumpinfo erase: - $(MSP430BSL) -e + $(MSP430BSL) -e $(app).c: config builddate appsfiles err $(app): $(libs) $(apps) diff --git a/firmware/apps/avr/avr.c b/firmware/apps/avr/avr.c index 168041f..c5d1929 100644 --- a/firmware/apps/avr/avr.c +++ b/firmware/apps/avr/avr.c @@ -6,9 +6,6 @@ #include "platform.h" #include "command.h" -#include -#include -#include #include "avr.h" //#include "glitch.h" @@ -43,10 +40,10 @@ void avrsetup(){ void avrconnect(){ //set I/O pins avrsetup(); //Cut this? - + SETSS; //delay(50); - + //Pulse !RST (SS) at least twice while CLK is low. CLRCLK; CLRSS; @@ -57,7 +54,7 @@ void avrconnect(){ //delay(5); CLRSS; //delay(5); - + //Enable programming avr_prgen(); } @@ -67,7 +64,7 @@ u8 avrtrans8(u8 byte){ register u16 bit; //This function came from the SPI Wikipedia article. //Minor alterations. - + for (bit = 0; bit < 8; bit++) { /* write MOSI on trailing edge of previous clock */ if (byte & 0x80) @@ -75,16 +72,16 @@ u8 avrtrans8(u8 byte){ else CLRMOSI; byte <<= 1; - + delay(2); SETCLK; - + /* read MISO on trailing edge */ byte |= READMISO; delay(2); CLRCLK; } - + return byte; } @@ -169,12 +166,12 @@ void avr_handle_fn( uint8_t const app, { unsigned long i, l; unsigned int at; - + /* if(!avr_isready() && connected) debugstr("AVR is not yet ready."); */ - + switch(verb){ case READ: case WRITE: @@ -231,7 +228,7 @@ void avr_handle_fn( uint8_t const app, //cmddata[0]=avr_peekflash(cmddataword[0]); //txdata(app,verb,1); at=cmddataword[0]; - + //Fetch large blocks for bulk fetches, //small blocks for individual peeks. l = len; diff --git a/firmware/apps/chipcon/chipcon.c b/firmware/apps/chipcon/chipcon.c index 96fec22..5785e2e 100644 --- a/firmware/apps/chipcon/chipcon.c +++ b/firmware/apps/chipcon/chipcon.c @@ -15,10 +15,6 @@ #include "command.h" #include "chipcon.h" -#include -#include -#include - //! Handles a chipcon command. void cc_handle_fn( uint8_t const app, uint8_t const verb, @@ -53,12 +49,12 @@ app_t const chipcon_app = { #if (platform == tilaunchpad) /* - * The Launchpad has only pins easily available + * The Launchpad has only pins easily available * P5.3 TCK SCK (labeled TEST J3-10 J2-17) DC closest to antenna (blue) * P5.2 IO MISO MOSI (labeled RST J3-8 J2-16) DD next to closer to USB (yellow) * P3.6 txd1 RST (labeled RXD J3-6 J1-4) next to GND, which is closest to USB (orange) * P3.7 rxd1 RST (labeled TXD J3-4 J1-3) connect to led1 J1-2 - * + * * for a permanent marriage between a TI-Launchpad, move RST to pin48 P5.4 * (requeries soldering) and use rxd/txd for direct communication with IM-ME dongle. */ @@ -80,7 +76,7 @@ app_t const chipcon_app = { #define CCSPEED 3 //#define CCSPEED 3 //#define CCDELAY(x) delay(x) -#define CCDELAY(x) +#define CCDELAY(x) #define SETMOSI SPIOUT|=MOSI #define CLRMOSI SPIOUT&=~MOSI @@ -125,7 +121,7 @@ void ccsetup(){ /* 33 cycle critical region 0000000e : e: f2 d0 0d 00 bis.b #13, &0x0031 ;5 cycles - 12: 31 00 + 12: 31 00 14: f2 c2 31 00 bic.b #8, &0x0031 ;4 cycles 18: d2 c3 31 00 bic.b #1, &0x0031 ;4 1c: f2 e2 31 00 xor.b #8, &0x0031 ;4 @@ -133,7 +129,7 @@ void ccsetup(){ 24: f2 e2 31 00 xor.b #8, &0x0031 ;4 28: f2 e2 31 00 xor.b #8, &0x0031 ;4 2c: d2 d3 31 00 bis.b #1, &0x0031 ;4 - 30: 30 41 ret + 30: 30 41 ret */ @@ -147,17 +143,17 @@ void ccdebuginit(){ #else SPIOUT|=MOSI+SCK+RST; #endif - + delay(30); //So the beginning is ready for glitching. - + //Two positive debug clock pulses while !RST is low. //Take RST low, pulse twice, then high. SPIOUT&=~SCK; delay(10); CLRRST; - + delay(10); - + //Two rising edges. SPIOUT^=SCK; //up delay(1); @@ -168,7 +164,7 @@ void ccdebuginit(){ SPIOUT^=SCK; //Unnecessary. delay(1); //delay(0); - + //Raise !RST. SETRST; } @@ -178,7 +174,7 @@ unsigned char cctrans8(unsigned char byte){ unsigned int bit; //This function came from the SPI Wikipedia article. //Minor alterations. - + for (bit = 0; bit < 8; bit++) { /* write MOSI on trailing edge of previous clock */ if (byte & 0x80) @@ -186,19 +182,19 @@ unsigned char cctrans8(unsigned char byte){ else CLRMOSI; byte <<= 1; - + /* half a clock cycle before leading/rising edge */ CCDELAY(CCSPEED>>2); SETCLK; - + /* half a clock cycle before trailing/falling edge */ CCDELAY(CCSPEED>>2); - + /* read MISO on trailing edge */ byte |= READMISO; CLRCLK; } - + return byte; } @@ -228,7 +224,7 @@ void cc_handle_fn( uint8_t const app, //ccdebuginit(); long i; int blocklen, blockadr; - + switch(verb){ //CC_PEEK and CC_POKE will come later. case PEEK: @@ -264,7 +260,7 @@ void cc_handle_fn( uint8_t const app, ccsetup(); txdata(app,verb,0); break; - + //Micro commands! case CC_CHIP_ERASE: case CC_MASS_ERASE_FLASH: @@ -330,13 +326,13 @@ void cc_handle_fn( uint8_t const app, if(len>2) blocklen=cmddataword[1]; blockadr=cmddataword[0]; - + //Return that many bytes. for(i=0;i> 8) / FLASH_WORD_SIZE) & 0x7E, - + //0x75, 0xAB, 0x23, //Set FWT per clock - 0x75, 0xAC, 0x00, // MOV FADDRL, #00; + 0x75, 0xAC, 0x00, // MOV FADDRL, #00; /* Erase page. */ - 0x75, 0xAE, 0x01, // MOV FLC, #01H; // ERASE - // ; Wait for flash erase to complete - 0xE5, 0xAE, // eraseWaitLoop: MOV A, FLC; - 0x20, 0xE7, 0xFB, // JB ACC_BUSY, eraseWaitLoop; - + 0x75, 0xAE, 0x01, // MOV FLC, #01H; // ERASE + // ; Wait for flash erase to complete + 0xE5, 0xAE, // eraseWaitLoop: MOV A, FLC; + 0x20, 0xE7, 0xFB, // JB ACC_BUSY, eraseWaitLoop; + /* End erase page. */ - // ; Initialize the data pointer - 0x90, 0xF0, 0x00, // MOV DPTR, #0F000H; - // ; Outer loops - 0x7F, HIBYTE_WORDS_PER_FLASH_PAGE, // MOV R7, #imm; - 0x7E, LOBYTE_WORDS_PER_FLASH_PAGE, // MOV R6, #imm; - 0x75, 0xAE, 0x02, // MOV FLC, #02H; // WRITE - // ; Inner loops + // ; Initialize the data pointer + 0x90, 0xF0, 0x00, // MOV DPTR, #0F000H; + // ; Outer loops + 0x7F, HIBYTE_WORDS_PER_FLASH_PAGE, // MOV R7, #imm; + 0x7E, LOBYTE_WORDS_PER_FLASH_PAGE, // MOV R6, #imm; + 0x75, 0xAE, 0x02, // MOV FLC, #02H; // WRITE + // ; Inner loops //24: - 0x7D, 0xde /*FLASH_WORD_SIZE*/, // writeLoop: MOV R5, #imm; - 0xE0, // writeWordLoop: MOVX A, @DPTR; - 0xA3, // INC DPTR; - 0xF5, 0xAF, // MOV FWDATA, A; - 0xDD, 0xFA, // DJNZ R5, writeWordLoop; - // ; Wait for completion - 0xE5, 0xAE, // writeWaitLoop: MOV A, FLC; - 0x20, 0xE6, 0xFB, // JB ACC_SWBSY, writeWaitLoop; - 0xDE, 0xF1, // DJNZ R6, writeLoop; - 0xDF, 0xEF, // DJNZ R7, writeLoop; - // ; Done, fake a breakpoint - 0xA5 // DB 0xA5; + 0x7D, 0xde /*FLASH_WORD_SIZE*/, // writeLoop: MOV R5, #imm; + 0xE0, // writeWordLoop: MOVX A, @DPTR; + 0xA3, // INC DPTR; + 0xF5, 0xAF, // MOV FWDATA, A; + 0xDD, 0xFA, // DJNZ R5, writeWordLoop; + // ; Wait for completion + 0xE5, 0xAE, // writeWaitLoop: MOV A, FLC; + 0x20, 0xE6, 0xFB, // JB ACC_SWBSY, writeWaitLoop; + 0xDE, 0xF1, // DJNZ R6, writeLoop; + 0xDF, 0xEF, // DJNZ R7, writeLoop; + // ; Done, fake a breakpoint + 0xA5 // DB 0xA5; }; @@ -543,18 +539,18 @@ const u8 flash_routine[] = { void cc_write_flash_page(u32 adr){ //Assumes that page has already been written to XDATA 0xF000 //debugstr("Flashing 2kb at 0xF000 to given adr."); - + if(adr&(MINFLASHPAGE_SIZE-1)){ debugstr("Flash page address is not on a page boundary. Aborting."); return; } - + if(flash_word_size!=2 && flash_word_size!=4){ debugstr("Flash word size is wrong, aborting write to"); debughex(adr); while(1); } - + //Routine comes next //WRITE_XDATA_MEMORY(IN: 0xF000 + FLASH_PAGE_SIZE, sizeof(routine), routine); cc_write_xdata(0xF000+MAXFLASHPAGE_SIZE, @@ -568,29 +564,29 @@ void cc_write_flash_page(u32 adr){ debugstr("Ugly patching code failing in chipcon.c"); cc_pokedatabyte(0xF000+MAXFLASHPAGE_SIZE+25, flash_word_size); - + //debugstr("Wrote flash routine."); - + //MOV MEMCTR, (bank * 16) + 1; cmddata[0]=0x75; cmddata[1]=0xc7; cmddata[2]=0x51; cc_debug_instr(3); //debugstr("Loaded bank info."); - + cc_set_pc(0xf000+MAXFLASHPAGE_SIZE);//execute code fragment cc_resume(); - + //debugstr("Executing."); - - + + while(!(cc_read_status()&CC_STATUS_CPUHALTED)){ - led_toggle();//blink LED while flashing + led_toggle();//blink LED while flashing } - - + + //debugstr("Done flashing."); - + led_off(); } @@ -599,7 +595,7 @@ unsigned short cc_get_pc(){ cmddata[0]=CCCMD_GET_PC; //0x28 cccmd(1); ccread(2); - + //Return the word. return cmddataword[0]; } @@ -675,12 +671,12 @@ unsigned char cc_peekcodebyte(unsigned long adr){ hb=(adr>>8)&0x7F, toret=0; adr&=0x7FFF; - + //MOV MEMCTR, (bank*16)+1 cc_debug(3, 0x75, 0xC7, (bank<<4) + 1); //MOV DPTR, address cc_debug(3, 0x90, hb, lb); - + //for each byte //CLR A cc_debug(2, 0xE4, 0, 0); @@ -688,7 +684,7 @@ unsigned char cc_peekcodebyte(unsigned long adr){ toret=cc_debug(3, 0x93, 0, 0); //INC DPTR //cc_debug(1, 0xA3, 0, 0); - + return toret; } @@ -699,14 +695,14 @@ unsigned char cc_pokedatabyte(unsigned int adr, unsigned char hb=(adr&0xFF00)>>8, lb=adr&0xFF; - + //MOV DPTR, adr cc_debug(3, 0x90, hb, lb); //MOV A, val cc_debug(2, 0x74, val, 0); //MOVX @DPTR, A cc_debug(1, 0xF0, 0, 0); - + return 0; /* DEBUG_INSTR(IN: 0x90, HIBYTE(address), LOBYTE(address), OUT: Discard); @@ -723,7 +719,7 @@ unsigned char cc_peekdatabyte(unsigned int adr){ unsigned char hb=(adr&0xFF00)>>8, lb=adr&0xFF; - + //MOV DPTR, adr cc_debug(3, 0x90, hb, lb); //MOVX A, @DPTR diff --git a/firmware/apps/radios/ccspi.c b/firmware/apps/radios/ccspi.c index df99ced..eb7417a 100644 --- a/firmware/apps/radios/ccspi.c +++ b/firmware/apps/radios/ccspi.c @@ -1,7 +1,7 @@ /*! \file ccspi.c \author Travis Goodspeed \brief Chipcon SPI Register Interface - + Unfortunately, there is very little similarity between the CC2420 and the CC2500, to name just two of the myriad of Chipcon SPI radios. Auto-detection will be a bit difficult, but more to the @@ -13,9 +13,6 @@ #include "platform.h" #include "command.h" #include //added for itoa -#include -#include -#include #include "ccspi.h" #include "spi.h" @@ -52,14 +49,14 @@ void ccspisetup(){ SPIDIR|=MOSI+SCK; DIRSS; DIRCE; - + P4OUT|=BIT5; //activate CC2420 voltage regulator msdelay(100); - + //Reset the CC2420. P4OUT&=~BIT6; P4OUT|=BIT6; - + //Begin a new transaction. CLRSS; SETSS; @@ -70,7 +67,7 @@ u8 ccspitrans8(u8 byte){ register unsigned int bit; //This function came from the CCSPI Wikipedia article. //Minor alterations. - + for (bit = 0; bit < 8; bit++) { /* write MOSI on trailing edge of previous clock */ if (byte & 0x80) @@ -78,14 +75,14 @@ u8 ccspitrans8(u8 byte){ else CLRMOSI; byte <<= 1; - + SETCLK; - + /* read MISO on trailing edge */ byte |= READMISO; CLRCLK; } - + return byte; } @@ -93,22 +90,22 @@ u8 ccspitrans8(u8 byte){ //! Writes a register u8 ccspi_regwrite(u8 reg, const u8 *buf, int len){ CLRSS; - + reg=ccspitrans8(reg); while(len--) ccspitrans8(*buf++); - + SETSS; return reg;//status } //! Reads a register u8 ccspi_regread(u8 reg, u8 *buf, int len){ CLRSS; - + reg=ccspitrans8(reg); while(len--) *buf++=ccspitrans8(0); - + SETSS; return reg;//status } @@ -118,9 +115,9 @@ void ccspi_handle_fn( uint8_t const app, uint8_t const verb, uint32_t const len){ unsigned long i; - + //debugstr("Chipcon SPI handler."); - + switch(verb){ case PEEK: cmddata[0]|=0x40; //Set the read bit. @@ -147,12 +144,12 @@ void ccspi_handle_fn( uint8_t const app, ccspitrans8(0x08); //SFLUSHRX SETSS; } - + //Is there a packet? if(FIFOP&&FIFO){ //Wait for completion. while(SFD); - + //Get the packet. CLRSS; ccspitrans8(CCSPI_RXFIFO | 0x40); @@ -161,7 +158,7 @@ void ccspi_handle_fn( uint8_t const app, for(i=0;i +#else #include #include #include +#endif #include "spi.h" @@ -52,10 +56,10 @@ void spisetup(){ SPIDIR|=MOSI+SCK+BIT0; //BIT0 might be SS SPIDIR&=~MISO; DIRSS; - + //Begin a new transaction. - - CLRSS; + + CLRSS; SETSS; } @@ -65,7 +69,7 @@ unsigned char spitrans8(unsigned char byte){ register unsigned int bit; //This function came from the SPI Wikipedia article. //Minor alterations. - + for (bit = 0; bit < 8; bit++) { /* write MOSI on trailing edge of previous clock */ if (byte & 0x80) @@ -73,11 +77,11 @@ unsigned char spitrans8(unsigned char byte){ else CLRMOSI; byte <<= 1; - + //SPIDELAY(100); SETCLK; //SPIDELAY(100); - + /* read MISO on trailing edge */ byte |= READMISO; CLRCLK; @@ -128,16 +132,16 @@ void spiflash_peekblock(unsigned long adr, unsigned char *buf, unsigned int len){ unsigned char i; - + SETSS; CLRSS; //Drop !SS to begin transaction. spitrans8(0x03);//Flash Read Command - + //Send address spitrans8((adr&0xFF0000)>>16); spitrans8((adr&0xFF00)>>8); spitrans8(adr&0xFF); - + for(i=0;i>16); spitrans8((adr&0xFF00)>>8); @@ -174,7 +178,7 @@ void spiflash_pokeblock(unsigned long adr, for(i=0;i0x100?0x100:len-off); @@ -212,14 +216,14 @@ void spiflash_peek(unsigned char app, len=3;//write 3 byte pointer for(i=0;i #ifdef MSP430 -#include +#ifdef __MSPGCC__ +#include +#else #include +#include #include -#include "msp430.h" +#endif + +void msp430_init(); +void led_init(); +void led_on(); +void led_off(); +void led_toggle(); #endif #include "config.h" diff --git a/firmware/ldscripts/msp430.x b/firmware/ldscripts/msp430.x new file mode 100644 index 0000000..67307ed --- /dev/null +++ b/firmware/ldscripts/msp430.x @@ -0,0 +1,203 @@ +/* Default linker script, for normal executables */ +OUTPUT_FORMAT("elf32-msp430") +OUTPUT_ARCH("msp430") +INCLUDE memory.x +INCLUDE periph.x +SECTIONS +{ + + /* Leave two blank bytes in ram for calibration data */ + .hack.dco_choice (NOLOAD) : { + SHORT(0) + } >REGION_DATA + /* Read-only sections, merged into text segment. */ + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .gnu.version : { *(.gnu.version) } + .gnu.version_d : { *(.gnu.version_d) } + .gnu.version_r : { *(.gnu.version_r) } + .rel.init : { *(.rel.init) } + .rela.init : { *(.rela.init) } + .rel.text : + { + *(.rel.text) + *(.rel.text.*) + *(.rel.gnu.linkonce.t*) + } + .rela.text : + { + *(.rela.text) + *(.rela.text.*) + *(.rela.gnu.linkonce.t*) + } + .rel.fini : { *(.rel.fini) } + .rela.fini : { *(.rela.fini) } + .rel.rodata : + { + *(.rel.rodata) + *(.rel.rodata.*) + *(.rel.gnu.linkonce.r*) + } + .rela.rodata : + { + *(.rela.rodata) + *(.rela.rodata.*) + *(.rela.gnu.linkonce.r*) + } + .rel.data : + { + *(.rel.data) + *(.rel.data.*) + *(.rel.gnu.linkonce.d*) + } + .rela.data : + { + *(.rela.data) + *(.rela.data.*) + *(.rela.gnu.linkonce.d*) + } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + /* Internal text space. */ + .text : + { + . = ALIGN(2); + KEEP(*(.init .init.*)) + KEEP(*(.init0)) /* Start here after reset. */ + KEEP(*(.init1)) /* User definable. */ + KEEP(*(.init2)) /* Initialize stack. */ + KEEP(*(.init3)) /* Initialize hardware, user definable. */ + KEEP(*(.init4)) /* Copy data to .data, clear bss. */ + KEEP(*(.init5)) /* User definable. */ + KEEP(*(.init6)) /* C++ constructors. */ + KEEP(*(.init7)) /* User definable. */ + KEEP(*(.init8)) /* User definable. */ + KEEP(*(.init9)) /* Call main(). */ + KEEP(*(.fini9)) /* Falls into here after main(). User definable. */ + KEEP(*(.fini8)) /* User definable. */ + KEEP(*(.fini7)) /* User definable. */ + KEEP(*(.fini6)) /* C++ destructors. */ + KEEP(*(.fini5)) /* User definable. */ + KEEP(*(.fini4)) /* User definable. */ + KEEP(*(.fini3)) /* User definable. */ + KEEP(*(.fini2)) /* User definable. */ + KEEP(*(.fini1)) /* User definable. */ + KEEP(*(.fini0)) /* Infinite loop after program termination. */ + KEEP(*(.fini .fini.*)) + . = ALIGN(2); + __ctors_start = . ; + KEEP(*(.ctors)) + __ctors_end = . ; + __dtors_start = . ; + KEEP(*(.dtors)) + __dtors_end = . ; + . = ALIGN(2); + *(.text .text.* .gnu.linkonce.t.*) + . = ALIGN(2); + } > REGION_TEXT + .rodata : + { + . = ALIGN(2); + *(.rodata .rodata.* .gnu.linkonce.r.*) + . = ALIGN(2); + } > REGION_TEXT + _etext = .; + .data : + { + . = ALIGN(2); + PROVIDE (__data_start = .) ; + *(.data) + *(SORT_BY_ALIGNMENT(.data.*)) + . = ALIGN(2); + *(.gnu.linkonce.d*) + . = ALIGN(2); + _edata = . ; + } > REGION_DATA AT > REGION_TEXT + PROVIDE (__data_load_start = LOADADDR(.data) ); + PROVIDE (__data_size = SIZEOF(.data) ); + .bss : + { + PROVIDE (__bss_start = .) ; + *(.bss) + *(SORT_BY_ALIGNMENT(.bss.*)) + *(COMMON) + PROVIDE (__bss_end = .) ; + _end = . ; + } > REGION_DATA + PROVIDE (__bss_size = SIZEOF(.bss) ); + .noinit : + { + PROVIDE (__noinit_start = .) ; + *(.noinit) + *(.noinit.*) + *(COMMON) + PROVIDE (__noinit_end = .) ; + _end = . ; + } > REGION_DATA + /* Information memory. */ + .infomem : + { + *(.infomem) + . = ALIGN(2); + *(.infomem.*) + } > infomem + .vectors : + { + PROVIDE (__vectors_start = .) ; + KEEP(*(.vectors*)) + _vectors_end = . ; + } > vectors + .fartext : + { + . = ALIGN(2); + *(.fartext) + . = ALIGN(2); + *(.fartext.*) + _efartext = .; + } > REGION_FAR_ROM + /* Stabs for profiling information*/ + .profiler 0 : { *(.profiler) } + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info) *(.gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* DWARF 3 */ + .debug_pubtypes 0 : { *(.debug_pubtypes) } + .debug_ranges 0 : { *(.debug_ranges) } + PROVIDE (__stack = ORIGIN(ram) + LENGTH(ram)); + PROVIDE (__data_start_rom = _etext); + PROVIDE (__data_end_rom = _etext + SIZEOF (.data)); +} diff --git a/firmware/lib/msp430.c b/firmware/lib/msp430.c index 1684f59..ec1a5c8 100644 --- a/firmware/lib/msp430.c +++ b/firmware/lib/msp430.c @@ -28,6 +28,7 @@ void led_off() } void led_toggle() { + PLEDOUT ^= PLEDPIN; } //! Initialize MSP430 registers and all that jazz. @@ -79,13 +80,13 @@ void msp430_init(){ #endif /** FIXME - + This part is really ugly. GSEL (P5.7) must be high to select normal voltage, but a lot of applications light to swing it low to be a nuissance. To get around this, we assume that anyone with a glitching FET will also have a DAC, then we set that DAC to a high voltage. - + At some point, each target must be sanitized to show that it doesn't clear P5OUT or P5DIR. */ diff --git a/firmware/lib/msp430x1612.c b/firmware/lib/msp430x1612.c index 9d28415..d577e50 100644 --- a/firmware/lib/msp430x1612.c +++ b/firmware/lib/msp430x1612.c @@ -2,31 +2,35 @@ #include "platform.h" +#ifdef __MSPGCC__ +#include +#else #include #include #include +#endif //! Receive a byte. unsigned char serial0_rx(){ char c; - + while(!(IFG1&URXIFG0));//wait for a byte c = RXBUF0; IFG1&=~URXIFG0; U0TCTL &= ~URXSE; - + return c; } //! Receive a byte. unsigned char serial1_rx(){ char c; - + while(!(IFG2&URXIFG1));//wait for a byte c = RXBUF1; IFG2&=~URXIFG1; U1TCTL &= ~URXSE; - + return c; } @@ -52,7 +56,7 @@ void serial1_tx(unsigned char x){ //! Set the baud rate. void setbaud0(unsigned char rate){ - + //http://mspgcc.sourceforge.net/baudrate.html switch(rate){ case 1://9600 baud @@ -100,15 +104,15 @@ void setbaud1(unsigned char rate){ void msp430_init_uart0(){ /* RS232 */ - + P3SEL |= BIT4|BIT5; // P3.4,5 = USART0 TXD/RXD P3DIR |= BIT4; - + UCTL0 = SWRST | CHAR; /* 8-bit character, UART mode */ UTCTL0 = SSEL1; /* UCLK = MCLK */ - + setbaud0(0); - + ME1 &= ~USPIE0; /* USART1 SPI module disable */ ME1 |= (UTXE0 | URXE0); /* Enable USART1 TXD/RXD */ @@ -116,24 +120,24 @@ void msp430_init_uart0(){ /* XXX Clear pending interrupts before enable!!! */ U0TCTL |= URXSE; - - + + //IE1 |= URXIE1; /* Enable USART1 RX interrupt */ } void msp430_init_uart1(){ - + /* RS232 */ P3DIR &= ~0x80; /* Select P37 for input (UART1RX) */ P3DIR |= 0x40; /* Select P36 for output (UART1TX) */ P3SEL |= 0xC0; /* Select P36,P37 for UART1{TX,RX} */ - + UCTL1 = SWRST | CHAR; /* 8-bit character, UART mode */ UTCTL1 = SSEL1; /* UCLK = MCLK */ - + setbaud1(0); - + ME2 &= ~USPIE1; /* USART1 SPI module disable */ ME2 |= (UTXE1 | URXE1); /* Enable USART1 TXD/RXD */ @@ -189,10 +193,10 @@ void msp430_init_dco() { #define DELTA ((MSP430_CPU_SPEED) / (32768 / 8)) unsigned int compare, oldcapture = 0; unsigned int i; - + WDTCTL = WDTPW + WDTHOLD; //stop WDT - - + + DCOCTL=0xF0; //a4 //1100 @@ -200,12 +204,12 @@ void msp430_init_dco() { /* ACLK is devided by 4. RSEL=6 no division for MCLK and SSMCLK. XT2 is off. */ //BCSCTL1 = 0xa8; - + BCSCTL2 = 0x00; /* Init FLL to desired frequency using the 32762Hz crystal DCO frquenzy = 2,4576 MHz */ - + PLEDOUT|=PLEDPIN; - + BCSCTL1 |= DIVA1 + DIVA0; /* ACLK = LFXT1CLK/8 */ for(i = 0xffff; i > 0; i--) { /* Delay for XTAL to settle */ asm("nop"); @@ -238,12 +242,12 @@ void msp430_init_dco() { /* -> Select next higher RSEL */ } } - + CCTL2 = 0; /* Stop CCR2 function */ TACTL = 0; /* Stop Timer_A */ BCSCTL1 &= ~(DIVA1 + DIVA0); /* remove /8 divisor from ACLK again */ - + PLEDOUT=~PLEDPIN; } diff --git a/firmware/lib/msp430x2618.c b/firmware/lib/msp430x2618.c index 947cf14..408e3ee 100644 --- a/firmware/lib/msp430x2618.c +++ b/firmware/lib/msp430x2618.c @@ -5,19 +5,23 @@ #include "platform.h" #include "dco_calib.h" - +#ifdef __MSPGCC__ +#include +#else #include #include #include +#endif + //! Receive a byte. unsigned char serial0_rx(){ char c; - + while(!(IFG2&UCA0RXIFG));//wait for a byte c = UCA0RXBUF; IFG2&=~UCA0RXIFG; - + //UCA0CTL1 &= ~UCA0RXSE; return c; } @@ -48,7 +52,7 @@ void serial1_tx(unsigned char x){ //! Set the baud rate. void setbaud0(unsigned char rate){ - + //Table 15-4, page 481 of 2xx Family Guide switch(rate){ case 1://9600 baud @@ -77,33 +81,33 @@ void setbaud0(unsigned char rate){ //! Set the baud rate of the second uart. void setbaud1(unsigned char rate){ - + } #define BAUD0EN 0x41 #define BAUD1EN 0x03 void msp430_init_uart(){ - + // Serial on P3.4, P3.5 P3SEL |= BIT4 + BIT5; P3DIR |= BIT4; - + //UCA0CTL1 |= UCSWRST; /* disable UART */ - + UCA0CTL0 = 0x00; //UCA0CTL0 |= UCMSB ; - + UCA0CTL1 |= UCSSEL_2; // SMCLK - + //UCA0BR0 = BAUD0EN; // 115200 //UCA0BR1 = BAUD1EN; setbaud(5);//default baud, 115200 - + UCA0MCTL = 0; // Modulation UCBRSx = 5 UCA0CTL1 &= ~UCSWRST; // **Initialize USCI state machine** - - + + //Leave this commented! //Interrupt is handled by target code, not by bootloader. //IE2 |= UCA0RXIE; @@ -120,17 +124,17 @@ void msp430_init_dco_done(){ void msp430_init_dco() { int i=1000; char *choice=(char *) 0x200; //First word of RAM. - + #ifdef __MSP430_HAS_PORT8__ P8SEL = 0; // disable XT2 on P8.7/8 #endif - + //Set P2.6 mode for MSP430F2274 #ifndef __MSP430_HAS_PORT5__ P2SEL = 0; //disable XIN on 2274 #endif - - + + #ifdef STATICDCO BCSCTL1 = (STATICDCO>>8); DCOCTL = (STATICDCO&0xFF); @@ -142,24 +146,24 @@ void msp430_init_dco() { }else{ /* Info is missing, guess at a good value. - + A list of correct calibrations in included as dco_calib.c, generated by script. */ DCOCTL = 0x00; //clear DCO - + BCSCTL1 = dco_calibrations[2*choice[0]+1]; DCOCTL = dco_calibrations[2*choice[0]]; choice[0]++; choice[0]%=dco_calibrations_count; } #endif - + //Minor delay. while(i--); - - - + + + return; } diff --git a/firmware/platforms/goodfet.h b/firmware/platforms/goodfet.h index e9ba90e..8e4249c 100644 --- a/firmware/platforms/goodfet.h +++ b/firmware/platforms/goodfet.h @@ -3,10 +3,13 @@ \brief Port descriptions for the GoodFET platform. */ +#ifdef __MSPGCC__ +#include +#else #include #include #include - +#endif //LED on P1.0 #define PLEDOUT P1OUT