From: travisutk <travisutk@12e2690d-a6be-4b82-a7b7-67c4a43b65c8>
Date: Sat, 17 Oct 2009 06:35:31 +0000 (+0000)
Subject: Chipcon refactoring, debugging.
X-Git-Url: http://git.rot13.org/?p=goodfet;a=commitdiff_plain;h=7d3404539568650baef6a21c85580ea8e3e097aa

Chipcon refactoring, debugging.

git-svn-id: https://svn.code.sf.net/p/goodfet/code/trunk@200 12e2690d-a6be-4b82-a7b7-67c4a43b65c8
---

diff --git a/client/GoodFETCC.py b/client/GoodFETCC.py
index bb96d30..d171f86 100644
--- a/client/GoodFETCC.py
+++ b/client/GoodFETCC.py
@@ -11,7 +11,6 @@ import binascii;
 from GoodFET import GoodFET;
 from intelhex import IntelHex;
 
-
 class GoodFETCC(GoodFET):
     """A GoodFET variant for use with Chipcon 8051 Zigbeema SoC."""
     def CChaltcpu(self):
diff --git a/firmware/apps/chipcon/chipcon.c b/firmware/apps/chipcon/chipcon.c
index 28440c4..1a4846b 100644
--- a/firmware/apps/chipcon/chipcon.c
+++ b/firmware/apps/chipcon/chipcon.c
@@ -7,8 +7,8 @@
 //This is like SPI, except that you read or write, not both.
 
 /* N.B. The READ verb performs a write of all (any) supplied data,
-    then reads a single byte reply from the target.  The WRITE verb
-    only writes.
+   then reads a single byte reply from the target.  The WRITE verb
+   only writes.
 */
 
 #include "platform.h"
@@ -21,10 +21,10 @@
 
 
 /* Concerning clock rates,
-    the maximimum clock rates are defined on page 4 of the spec.
-    They vary, but are roughly 30MHz.  Raising this clock rate might
-    allow for clock glitching, but the GoodFET isn't sufficient fast for that.
-    Perhaps a 200MHz ARM or an FPGA in the BadassFET?
+   the maximimum clock rates are defined on page 4 of the spec.
+   They vary, but are roughly 30MHz.  Raising this clock rate might
+   allow for clock glitching, but the GoodFET isn't sufficient fast for that.
+   Perhaps a 200MHz ARM or an FPGA in the BadassFET?
 */
 
 //Pins and I/O
@@ -230,30 +230,29 @@ void cchandle(unsigned char app,
 
 //! Erase all of a Chipcon's memory.
 void cc_chip_erase(){
-  cmddata[0]=0x14;
+  cmddata[0]=CCCMD_CHIP_ERASE; //0x14
   cccmd(1);
   ccread(1);
 }
 //! Write the configuration byte.
 void cc_wr_config(unsigned char config){
-  cmddata[0]=0x1d;
+  cmddata[0]=CCCMD_WR_CONFIG; //0x1D
   cmddata[1]=config;
   cccmd(2);
   ccread(1);
 }
 //! Read the configuration byte.
 unsigned char cc_rd_config(){
-  cmddata[0]=0x24;
+  cmddata[0]=CCCMD_RD_CONFIG; //0x24
   cccmd(1);
   ccread(1);
   return cmddata[0];
 }
 
 
-
 //! Read the status register
 unsigned char cc_read_status(){
-  cmddata[0]=0x34;
+  cmddata[0]=CCCMD_READ_STATUS; //0x3f
   cccmd(1);
   ccread(1);
   return cmddata[0];
@@ -262,7 +261,7 @@ unsigned char cc_read_status(){
 //! Read the CHIP ID bytes.
 unsigned short cc_get_chip_id(){
   unsigned short toret;
-  cmddata[0]=0x68;
+  cmddata[0]=CCCMD_GET_CHIP_ID; //0x68
   cccmd(1);
   ccread(2);
   
@@ -275,7 +274,7 @@ unsigned short cc_get_chip_id(){
 
 //! Read the PC
 unsigned short cc_get_pc(){
-  cmddata[0]=0x28;
+  cmddata[0]=CCCMD_GET_PC; //0x28
   cccmd(1);
   ccread(2);
   
@@ -285,6 +284,7 @@ unsigned short cc_get_pc(){
 
 //! Set a hardware breakpoint.
 void cc_set_hw_brkpnt(unsigned short adr){
+  debugstr("FIXME: This certainly won't work.");
   cmddataword[0]=adr;
   cccmd(2);
   ccread(1);
@@ -294,14 +294,14 @@ void cc_set_hw_brkpnt(unsigned short adr){
 
 //! Halt the CPU.
 void cc_halt(){
-  cmddata[0]=0x44;
+  cmddata[0]=CCCMD_HALT; //0x44
   cccmd(1);
   ccread(1);
   return;
 }
 //! Resume the CPU.
 void cc_resume(){
-  cmddata[0]=0x4C;
+  cmddata[0]=CCCMD_RESUME; //0x4C
   cccmd(1);
   ccread(1);
   return;
@@ -310,7 +310,7 @@ void cc_resume(){
 
 //! Step an instruction
 void cc_step_instr(){
-  cmddata[0]=0x5C;
+  cmddata[0]=CCCMD_STEP_INSTR; //0x5C
   cccmd(1);
   ccread(1);
   return;
@@ -319,7 +319,7 @@ void cc_step_instr(){
 //! Debug an instruction.
 void cc_debug_instr(unsigned char len){
   //Bottom two bits of command indicate length.
-  unsigned char cmd=0x54+(len&0x3);
+  unsigned char cmd=CCCMD_DEBUG_INSTR+(len&0x3); //0x54+len
   CCWRITE;
   cctrans8(cmd);  //Second command code
   cccmd(len&0x3); //Command itself.
@@ -332,13 +332,8 @@ unsigned char cc_debug(unsigned char len,
 	      unsigned char a,
 	      unsigned char b,
 	      unsigned char c){
-  unsigned char cmd=0x54+(len&0x3);//(len&0x3);
+  unsigned char cmd=CCCMD_DEBUG_INSTR+(len&0x3);//0x54+len
   CCWRITE;
-  cctrans8(0xFF);//resync
-  cctrans8(0xFF);//resync
-  cctrans8(0xFF);//resync
-  cctrans8(0xFF);//resync
-  cctrans8(0xFF);//resync
   cctrans8(cmd);
   if(len--)
     cctrans8(a);
diff --git a/firmware/apps/jtag/jtag430.c b/firmware/apps/jtag/jtag430.c
index 0d1fbfb..1275def 100644
--- a/firmware/apps/jtag/jtag430.c
+++ b/firmware/apps/jtag/jtag430.c
@@ -281,6 +281,19 @@ void jtag430handle(unsigned char app,
   
   //debugstr("Classic MSP430 handler.");
   
+  
+  /* FIXME
+   * Sometimes JTAG doesn't init correctly.
+   * This restarts the connection if the masked-rom
+   * chip ID cannot be read.  Should print warning
+   * for testing server.
+   */
+  while((i=jtag430_readmem(0xff0))==0xFFFF){
+    jtag430_start();
+    P1OUT^=1;
+  }
+  P1OUT&=~1;
+    
   switch(verb){
   case START:
     //Enter JTAG mode.
diff --git a/firmware/apps/jtag/jtag430x2.c b/firmware/apps/jtag/jtag430x2.c
index 1acc6e1..bdba2cb 100644
--- a/firmware/apps/jtag/jtag430x2.c
+++ b/firmware/apps/jtag/jtag430x2.c
@@ -27,12 +27,12 @@ unsigned char jtag430x2_start(){
   
   //Entry sequence from Page 67 of SLAU265A for 4-wire MSP430 JTAG
   CLRRST;
-  delay(10);//10
+  delay(20);//10
   CLRTST;
 
-  delay(5);//5
+  delay(10);//5
   SETTST;
-  msdelay(5);//5
+  msdelay(10);//5
   SETRST;
   P5DIR&=~RST;
   
@@ -210,6 +210,13 @@ void jtag430x2handle(unsigned char app,
     if(jtagid==MSP430JTAGID){ 
       jtag430mode=MSP430MODE;
       drwidth=16;
+      
+      //Perform a reset and disable watchdog.
+      jtag430_por();
+      jtag430_writemem(0x120,0x5a80);//disable watchdog
+      
+      jtag430_haltcpu();
+      
       jtag430_resettap();
       txdata(app,verb,1);
       return;
diff --git a/firmware/include/chipcon.h b/firmware/include/chipcon.h
index 31f375d..dd96f81 100644
--- a/firmware/include/chipcon.h
+++ b/firmware/include/chipcon.h
@@ -4,6 +4,18 @@
 */
 
 
+//Chipcon command definitions.
+#define CCCMD_CHIP_ERASE 0x14
+#define CCCMD_WR_CONFIG 0x1D
+#define CCCMD_RD_CONFIG 0x24
+#define CCCMD_READ_STATUS 0x34
+#define CCCMD_GET_CHIP_ID 0x68
+#define CCCMD_GET_PC 0x28
+#define CCCMD_HALT 0x44
+#define CCCMD_RESUME 0x4C
+#define CCCMD_STEP_INSTR 0x5C
+#define CCCMD_DEBUG_INSTR 0x54
+
 //! Erase a chipcon chip.
 void cc_chip_erase();
 //! Write the configuration byte.