From: travisutk <travisutk@12e2690d-a6be-4b82-a7b7-67c4a43b65c8>
Date: Sun, 28 Feb 2010 01:17:44 +0000 (+0000)
Subject: I/O stuff.
X-Git-Url: http://git.rot13.org/?p=goodfet;a=commitdiff_plain;h=83a29da6187d81430105b48abee72b7a59084369;ds=sidebyside

I/O stuff.

git-svn-id: https://svn.code.sf.net/p/goodfet/code/trunk@364 12e2690d-a6be-4b82-a7b7-67c4a43b65c8
---

diff --git a/firmware/apps/glitch/glitch.c b/firmware/apps/glitch/glitch.c
index f337e42..6e63b91 100644
--- a/firmware/apps/glitch/glitch.c
+++ b/firmware/apps/glitch/glitch.c
@@ -29,9 +29,9 @@ void glitchsetup(){
   //Set GSEL high to disable glitching.
   
   //Normal voltage, use resistors instead of output.
-  P5DIR=0x80;   //ONLY glitch pin is output.
+  //P5DIR=0x80;   //ONLY glitch pin is output.
   P5OUT|=0x80;  //It MUST begin high.
-  P5REN|=0xFF;  //Resistors pull high and low weakly.
+  //P5REN|=0x7F;  //Resistors pull high and low weakly.
   
   P6DIR|=BIT6+BIT5;
   P6OUT|=BIT6+BIT5;
@@ -41,7 +41,6 @@ void glitchsetup(){
   CCTL0 = CCIE;                         // CCR0 interrupt enabled
   CCR0 = glitchcount+0x15; //clock divider
   TACTL |= MC_3;
-  _EINT();                              // Enable interrupts 
 #endif
 }
 
@@ -51,7 +50,6 @@ interrupt(TIMERA0_VECTOR) Timer_A (void){
   //P5DIR=BIT7; //All else high impedance.
   P5OUT|=BIT7;//Normal
   TACTL |= MC0;// Stop Timer_A;
-  
   return;
 }