From 42c0903e02d7f9e6c26e7b53faa0961e9c2f0aeb Mon Sep 17 00:00:00 2001 From: travisutk Date: Sun, 4 Oct 2009 10:31:22 +0000 Subject: [PATCH] MSP430 Erase is no longer as harsh. In JTAG430_WRITEFLASH, the write is attempted twice if unsuccessful the first time. git-svn-id: https://svn.code.sf.net/p/goodfet/code/trunk@172 12e2690d-a6be-4b82-a7b7-67c4a43b65c8 --- firmware/apps/jtag/jtag430.c | 14 +++++++++----- firmware/apps/jtag/jtag430asm.S | 6 +++++- 2 files changed, 14 insertions(+), 6 deletions(-) diff --git a/firmware/apps/jtag/jtag430.c b/firmware/apps/jtag/jtag430.c index 821b655..f48db81 100644 --- a/firmware/apps/jtag/jtag430.c +++ b/firmware/apps/jtag/jtag430.c @@ -113,7 +113,6 @@ void jtag430_writeflashword(unsigned int adr, unsigned int data){ //Pulse TCLK jtag430_tclk_flashpulses(35); //35 standard - } //! Configure flash, then write a word. @@ -346,13 +345,18 @@ void jtag430handle(unsigned char app, case JTAG430_WRITEFLASH: //debugstr("Poking flash memory."); jtag430_writeflash(cmddataword[0],cmddataword[2]); + + //Try again if failure. + if(cmddataword[0]!=jtag430_readmem(cmddataword[0])) + jtag430_writeflash(cmddataword[0],cmddataword[2]); + + //Return result. cmddataword[0]=jtag430_readmem(cmddataword[0]); + txdata(app,verb,2); break; case JTAG430_ERASEFLASH: - jtag430_eraseflash(ERASE_MASS,0xFFFE,0xFFFF); - jtag430_eraseflash(ERASE_MASS,0xFFFE,0xFFFF); - jtag430_eraseflash(ERASE_MASS,0xFFFE,0xFFFF); + jtag430_eraseflash(ERASE_MASS,0xFFFE,0x3000); txdata(app,verb,0); break; case JTAG430_SETPC: @@ -371,5 +375,5 @@ void jtag430handle(unsigned char app, default: jtaghandle(app,verb,len); } - //jtag430_resettap(); + //jtag430_resettap(); //DO NOT UNCOMMENT } diff --git a/firmware/apps/jtag/jtag430asm.S b/firmware/apps/jtag/jtag430asm.S index 672d0ee..5bbf352 100644 --- a/firmware/apps/jtag/jtag430asm.S +++ b/firmware/apps/jtag/jtag430asm.S @@ -12,10 +12,14 @@ jtag430_tclk_flashpulses: // At 16MHz, 33 to 62 cycles/loop are allowed. jtag430_tclk_flashpulses_3mhz: mov #0x0031, r14 -pulseloop3: +pulseloop3: bis.b #2, @r14 ;SETTCLK, 3 cycles sub #1, r15 ; 1 cycle ;; 1+3+3+1+2=10, within limits + nop + nop + nop ;10+3=13 + bic.b #2, @r14 ;CLRTCLK, 3 cycles tst r15 ; 1 cycle jnz pulseloop3 ; 2 cycles -- 2.20.1