From 74ab06d026d20e3c13cd2bcb1ac89d83d79fbf5f Mon Sep 17 00:00:00 2001
From: travisutk <travisutk@12e2690d-a6be-4b82-a7b7-67c4a43b65c8>
Date: Sat, 8 Aug 2009 20:00:59 +0000
Subject: [PATCH 1/1] Beginning support for the second UART.

git-svn-id: https://svn.code.sf.net/p/goodfet/code/trunk@73 12e2690d-a6be-4b82-a7b7-67c4a43b65c8
---
 firmware/apps/chipcon/chipcon.c |  3 +--
 firmware/apps/jtag/jtag430asm.S |  2 +-
 firmware/include/platform.h     | 11 +++++---
 firmware/lib/msp430f1612.c      | 48 +++++++++++++++++++++++++++++++--
 4 files changed, 56 insertions(+), 8 deletions(-)

diff --git a/firmware/apps/chipcon/chipcon.c b/firmware/apps/chipcon/chipcon.c
index 3aebe1e..ad701be 100644
--- a/firmware/apps/chipcon/chipcon.c
+++ b/firmware/apps/chipcon/chipcon.c
@@ -215,7 +215,6 @@ void cchandle(unsigned char app,
     txdata(app,verb,1);
     break;
   case CC_SET_PC:
-    
   case CC_CLOCK_INIT:
   case CC_WRITE_FLASH_PAGE:
   case CC_MASS_ERASE_FLASH:
@@ -360,7 +359,7 @@ unsigned char cc_peekcodebyte(unsigned long adr){
   //CLR A
   cc_debug(2, 0xE4, 0, 0);
   //MOVC A, @A+DPTR;
-  toret=cc_debug(1, 0x93, 0, 0);
+  toret=cc_debug(3, 0x93, 0, 0);
   //INC DPTR
   //cc_debug(1, 0xA3, 0, 0);
   
diff --git a/firmware/apps/jtag/jtag430asm.S b/firmware/apps/jtag/jtag430asm.S
index 5c7caa2..e9fa6f5 100644
--- a/firmware/apps/jtag/jtag430asm.S
+++ b/firmware/apps/jtag/jtag430asm.S
@@ -1,5 +1,5 @@
 .globl jtag430_tclk_flashpulses
-.type jtag430_tclk_flashpulses,@function    /* declare main as a function */
+.type jtag430_tclk_flashpulses,@function //for linking
 
 
 //! At 3.68MHz, 7 to 14 cycles/loop are allowed for 257 to 475kHz
diff --git a/firmware/include/platform.h b/firmware/include/platform.h
index b315d90..f7e9246 100644
--- a/firmware/include/platform.h
+++ b/firmware/include/platform.h
@@ -1,10 +1,17 @@
 //! \file platform.h
 
-
 unsigned char serial_rx();
 void serial_tx(unsigned char);
+
+unsigned char serial1_rx();
+void serial1_tx(unsigned char);
+
 void setbaud(unsigned char);
+void setbaud1(unsigned char);
+
+//! Initialize the UART
 void msp430_init_uart();
+//! Initialize the DCO Clock
 void msp430_init_dco();
 
 //LED on P1.0
@@ -12,5 +19,3 @@ void msp430_init_dco();
 #define PLEDDIR P1DIR
 #define PLEDPIN 0x1
 
-
-
diff --git a/firmware/lib/msp430f1612.c b/firmware/lib/msp430f1612.c
index 58797ed..e1d03a7 100644
--- a/firmware/lib/msp430f1612.c
+++ b/firmware/lib/msp430f1612.c
@@ -18,12 +18,32 @@ unsigned char serial_rx(){
   
   return c;
 }
+
+//! Receive a byte.
+unsigned char serial1_rx(){
+  char c;
+  
+  while(!(IFG2&URXIFG1));//wait for a byte
+  c = RXBUF1;
+  IFG2&=~URXIFG1;
+  U1TCTL &= ~URXSE;
+  
+  return c;
+}
+
+
 //! Transmit a byte.
 void serial_tx(unsigned char x){
   while ((IFG1 & UTXIFG0) == 0); //loop until buffer is free
   TXBUF0 = x;
 }
 
+//! Transmit a byte on the second UART.
+void serial1_tx(unsigned char x){
+  while ((IFG2 & UTXIFG1) == 0); //loop until buffer is free
+  TXBUF1 = x;
+}
+
 //! Set the baud rate.
 void setbaud(unsigned char rate){
   
@@ -48,9 +68,32 @@ void setbaud(unsigned char rate){
   }
 }
 
-void msp430_init_uart(){
+//! Set the baud rate of the second uart.
+void setbaud1(unsigned char rate){
   
-  /* RS232 */
+  //http://mspgcc.sourceforge.net/baudrate.html
+  switch(rate){
+  case 1://9600 baud
+    UBR01=0x7F; UBR11=0x01; UMCTL1=0x5B; /* uart0 3683400Hz 9599bps */
+    break;
+  case 2://19200 baud
+    UBR01=0xBF; UBR11=0x00; UMCTL1=0xF7; /* uart0 3683400Hz 19194bps */
+    break;
+  case 3://38400 baud
+    UBR01=0x5F; UBR11=0x00; UMCTL1=0xBF; /* uart0 3683400Hz 38408bps */
+    break;
+  case 4://57600 baud
+    UBR01=0x40; UBR11=0x00; UMCTL1=0x00; /* uart0 3683400Hz 57553bps */
+    break;
+  default:
+  case 5://115200 baud
+    UBR01=0x20; UBR11=0x00; UMCTL1=0x00; /* uart0 3683400Hz 115106bps */
+    break;
+  }
+}
+
+
+void msp430_init_uart(){
   
   P3SEL |= BIT4|BIT5;                        // P3.4,5 = USART0 TXD/RXD
   P3DIR |= BIT4;
@@ -60,6 +103,7 @@ void msp430_init_uart(){
   
   setbaud(0);
   
+  //Necessary for bit-banging, switch to hardware for performance.
   ME1 &= ~USPIE0;			/* USART1 SPI module disable */
   ME1 |= (UTXE0 | URXE0);               /* Enable USART1 TXD/RXD */
 
-- 
2.20.1