From a456d2fbf645904f642f714fa86766f195384d94 Mon Sep 17 00:00:00 2001
From: travisutk <travisutk@12e2690d-a6be-4b82-a7b7-67c4a43b65c8>
Date: Tue, 16 Feb 2010 21:54:42 +0000
Subject: [PATCH] New Chipcon library stuff.

git-svn-id: https://svn.code.sf.net/p/goodfet/code/trunk@329 12e2690d-a6be-4b82-a7b7-67c4a43b65c8
---
 client/GoodFET.py               |  6 ++++++
 client/GoodFETAVR.py            |  7 +------
 client/GoodFETCC.py             | 11 ++++++++++-
 firmware/apps/chipcon/chipcon.c |  5 +++++
 firmware/apps/glitch/glitch.c   |  6 +++---
 5 files changed, 25 insertions(+), 10 deletions(-)

diff --git a/client/GoodFET.py b/client/GoodFET.py
index 654995b..1eb8575 100755
--- a/client/GoodFET.py
+++ b/client/GoodFET.py
@@ -124,6 +124,12 @@ class GoodFET:
         self.data=[app&0xff, verb&0xFF]+data;
         self.writecmd(self.GLITCHAPP,0x81,len(self.data),self.data);
         #return ord(self.data[0]);
+    def glitchstart(self):
+        """Glitch into the AVR application."""
+        self.glitchVerb(self.APP,0x20,None);
+    def glitchstarttime(self):
+        """Measure the timer of the START verb."""
+        return self.glitchTime(self.APP,0x20,None);
     def glitchTime(self,app,verb,data):
         """Time the execution of a verb."""
         if data==None: data=[];
diff --git a/client/GoodFETAVR.py b/client/GoodFETAVR.py
index d950b53..c0af361 100644
--- a/client/GoodFETAVR.py
+++ b/client/GoodFETAVR.py
@@ -11,6 +11,7 @@ from GoodFET import GoodFET;
 
 class GoodFETAVR(GoodFET):
     AVRAPP=0x32;
+    APP=AVRAPP;
     AVRVendors={0x1E: "Atmel",
                 0x00: "Locked",
                 };
@@ -67,12 +68,6 @@ class GoodFETAVR(GoodFET):
     def start(self):
         """Start the connection."""
         self.writecmd(self.AVRAPP,0x20,0,None);
-    def glitchstart(self):
-        """Glitch into the AVR application."""
-        self.glitchVerb(self.AVRAPP,0x20,None);
-    def glitchstarttime(self):
-        """Measure the timer of the START verb."""
-        return self.glitchTime(self.AVRAPP,0x20,None);
     def forcestart(self):
         """Forcibly start a connection."""
         
diff --git a/client/GoodFETCC.py b/client/GoodFETCC.py
index b700131..83d0b9f 100644
--- a/client/GoodFETCC.py
+++ b/client/GoodFETCC.py
@@ -13,6 +13,8 @@ from intelhex import IntelHex;
 
 class GoodFETCC(GoodFET):
     """A GoodFET variant for use with Chipcon 8051 Zigbeema SoC."""
+    APP=0x30;
+    
     def CChaltcpu(self):
         """Halt the CPU."""
         self.writecmd(0x30,0x86,0,self.data);
@@ -72,6 +74,9 @@ class GoodFETCC(GoodFET):
     def CClockchip(self):
         """Set the flash lock bit in info mem."""
         self.writecmd(0x30, 0x9A, 0, None);
+    def lock(self):
+        """Set the flash lock bit in info mem."""
+        self.CClockchip();
     
 
     CCversions={0x0100:"CC1110",
@@ -162,6 +167,10 @@ class GoodFETCC(GoodFET):
     def CCchiperase(self):
         """Erase all of the target's memory."""
         self.writecmd(0x30,0x80,0,None);
+    def erase(self):
+        """Erase all of the target's memory."""
+        self.CCchiperase();
+    
     def CCstatus(self):
         """Check the status."""
         self.writecmd(0x30,0x84,0,None);
@@ -197,7 +206,7 @@ class GoodFETCC(GoodFET):
         """Start debugging."""
         self.writecmd(0x30,0x20,0,self.data);
         ident=self.CCidentstr();
-        print "Target identifies as %s." % ident;
+        #print "Target identifies as %s." % ident;
         #print "Status: %s." % self.CCstatusstr();
         self.CCreleasecpu();
         self.CChaltcpu();
diff --git a/firmware/apps/chipcon/chipcon.c b/firmware/apps/chipcon/chipcon.c
index 6c910e7..c2c2a27 100644
--- a/firmware/apps/chipcon/chipcon.c
+++ b/firmware/apps/chipcon/chipcon.c
@@ -53,10 +53,15 @@ void ccsetup(){
   P5OUT|=MOSI+SCK+RST;
   P5DIR|=MOSI+SCK+RST;
   //P5DIR&=~MISO;  //MOSI is MISO
+  
+  //P5REN=0xFF;
+  
 }
 
 //! Initialize the debugger
 void ccdebuginit(){
+  delay(30); //So the beginning is ready for glitching.
+  
   //Two positive debug clock pulses while !RST is low.
   //Take RST low, pulse twice, then high.
   P5OUT&=~SCK;
diff --git a/firmware/apps/glitch/glitch.c b/firmware/apps/glitch/glitch.c
index df7dc86..56de8c3 100644
--- a/firmware/apps/glitch/glitch.c
+++ b/firmware/apps/glitch/glitch.c
@@ -37,7 +37,7 @@ void glitchsetup(){
   WDTCTL = WDTPW + WDTHOLD;             // Stop WDT
   TACTL = TASSEL1 + TACLR;              // SMCLK, clear TAR
   CCTL0 = CCIE;                         // CCR0 interrupt enabled
-  CCR0 = glitchcount+0x30; //clock divider
+  CCR0 = glitchcount+0x15; //clock divider
   TACTL |= MC_3;
   _EINT();                              // Enable interrupts 
 #endif
@@ -46,11 +46,11 @@ void glitchsetup(){
 // Timer A0 interrupt service routine
 interrupt(TIMERA0_VECTOR) Timer_A (void)
 {
-  P1OUT^=1;
   P5OUT&=~BIT7;//Glitch
+  //P5DIR=BIT7; //All else high impedance.
   P5OUT|=BIT7;//Normal
   TACTL |= MC0;// Stop Timer_A;
-  P1OUT&=~1;
+  
   return;
 }
 
-- 
2.20.1