From e8fe7534c5f3ad2e281669bd0f869b8327761861 Mon Sep 17 00:00:00 2001 From: dodge-this Date: Thu, 7 Feb 2013 12:30:24 +0000 Subject: [PATCH] jtagarm: added jtag_trans_many and supporting firmware and client functions/protocol, allowing greater control over arbitrary size scan chains (currently DR is the focus). LSB portion is working and relatively well-tested using IDCODE and shifting 41 bits. still have to true up the MSB part. git-svn-id: https://svn.code.sf.net/p/goodfet/code/trunk@1465 12e2690d-a6be-4b82-a7b7-67c4a43b65c8 --- client/GoodFETARM7.py | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/client/GoodFETARM7.py b/client/GoodFETARM7.py index 5a23466..3807e64 100644 --- a/client/GoodFETARM7.py +++ b/client/GoodFETARM7.py @@ -48,6 +48,8 @@ EICE_WRITE = 0x96 SCAN_N_SIZE = 0x9e IR_SIZE = 0x9f +DR_SHIFT_MANY = 0x9c + IR_EXTEST = 0x0 IR_SCAN_N = 0x2 IR_SAMPLE = 0x3 @@ -277,6 +279,40 @@ class GoodFETARM7(GoodFET): self.writecmd(0x13,DR_SHIFT_MORE,14,[bits&0xff, flags&0xff, 0, 0, data&0xff,(data>>8)&0xff,(data>>16)&0xff,(data>>24)&0xff, (data>>32)&0xff,(data>>40)&0xff,(data>>48)&0xff,(data>>56)&0xff,(data>>64)&0xff,(data>>72)&0xff]) return self.data + def ARMshift_DR_many(self, data, bits, flags): + darry = [] + tbits = bits + + # this is LSB, least sig BYTE first, between here and goodfet firmware + while (tbits>0): + darry.append( data&0xff ) + data >>= 8 + tbits -= 8 + + # bitcount, flags, [data] + data = [ bits&0xff, flags&0xff ] + data.extend(darry) + #print data + + self.writecmd(0x13,DR_SHIFT_MANY, len(darry)+2, data ) + + #print repr(self.data[2:]) + data = self.data[2:] + print repr(data) + out = 0 + tbits = bits + + # peal it off LSB again.... + while (tbits>0): + #print tbits + out <<= 8 + out += ord(data[-1]) + data = data[:-1] + #print hex(out) + tbits -= 8 + + return out + def ARMwaitDBG(self, timeout=0xff): self.current_dbgstate = self.ARMget_dbgstate() while ( not ((self.current_dbgstate & 9L) == 9)): -- 2.20.1