use defined hexdump istead of rfid_hexdump

[librfid] / src / rc632.h

diff --git a/src/rc632.h b/src/rc632.h
index 4ad0e99..49e1c4d 100644 (file)
--- a/src/rc632.h
+++ b/src/rc632.h
@@ -67,6 +67,22 @@ enum rc632_registers {
        RC632_REG_TEST_DIGI_SELECT      = 0x3d,
 };
 
+enum rc632_reg_status {
+       RC632_STAT_LOALERT              = 0x01,
+       RC632_STAT_HIALERT              = 0x02,
+       RC632_STAT_ERR                  = 0x04,
+       RC632_STAT_IRQ                  = 0x08,
+#define RC632_STAT_MODEM_MASK          0x70
+       RC632_STAT_MODEM_IDLE           = 0x00,
+       RC632_STAT_MODEM_TXSOF          = 0x10,
+       RC632_STAT_MODEM_TXDATA         = 0x20,
+       RC632_STAT_MODEM_TXEOF          = 0x30,
+       RC632_STAT_MODEM_GOTORX         = 0x40,
+       RC632_STAT_MODEM_PREPARERX      = 0x50,
+       RC632_STAT_MODEM_AWAITINGRX     = 0x60,
+       RC632_STAT_MODEM_RECV           = 0x70,
+};
+
 enum rc632_reg_command {
        RC632_CMD_IDLE                  = 0x00,
        RC632_CMD_WRITE_E2              = 0x01,
@@ -79,13 +95,27 @@ enum rc632_reg_command {
        RC632_CMD_RECEIVE               = 0x16,
        RC632_CMD_LOAD_KEY              = 0x19,
        RC632_CMD_TRANSMIT              = 0x1a,
-       RC632_CMD_TRANSCIEVE            = 0x1e,
+       RC632_CMD_TRANSCEIVE            = 0x1e,
        RC632_CMD_STARTUP               = 0x3f,
 };
 
+enum rc632_reg_interrupt {
+       RC632_INT_LOALERT               = 0x01,
+       RC632_INT_HIALERT               = 0x02,
+       RC632_INT_IDLE                  = 0x04,
+       RC632_INT_RX                    = 0x08,
+       RC632_INT_TX                    = 0x10,
+       RC632_INT_TIMER                 = 0x20,
+       RC632_INT_SET                   = 0x80,
+};
+
 enum rc632_reg_control {
+       RC632_CONTROL_FIFO_FLUSH        = 0x01,
+       RC632_CONTROL_TIMER_START       = 0x02,
+       RC632_CONTROL_TIMER_STOP        = 0x04,
        RC632_CONTROL_CRYPTO1_ON        = 0x08,
        RC632_CONTROL_POWERDOWN         = 0x10,
+       RC632_CONTROL_STANDBY           = 0x20,
 };
 
 enum rc632_reg_error_flag {
@@ -112,22 +142,27 @@ enum rc632_reg_tx_control {
 };
 
 enum rc632_reg_coder_control {
+        /* bit 2-0 TXCoding */
+#define RC632_CDRCTRL_TXCD_MASK                0x07
        RC632_CDRCTRL_TXCD_NRZ          = 0x00,
        RC632_CDRCTRL_TXCD_14443A       = 0x01,
        RC632_CDRCTRL_TXCD_ICODE_STD    = 0x04,
+       RC632_CDRCTRL_TXCD_ICODE_FAST   = 0x05,
+       RC632_CDRCTRL_TXCD_15693_STD    = 0x06,
+       RC632_CDRCTRL_TXCD_15693_FAST   = 0x07,
 
+       /* bit5-3 CoderRate*/
+#define RC632_CDRCTRL_RATE_MASK                0x38
        RC632_CDRCTRL_RATE_848K         = 0x00,
-#if 0
-       /* See mc073930.pdf, page 41 */
-       RC632_CDRCTRL_RATE_424K         = 0x80,
-#else
        RC632_CDRCTRL_RATE_424K         = 0x08,
-#endif
        RC632_CDRCTRL_RATE_212K         = 0x10,
        RC632_CDRCTRL_RATE_106K         = 0x18,
        RC632_CDRCTRL_RATE_14443B       = 0x20,
        RC632_CDRCTRL_RATE_15693        = 0x28,
        RC632_CDRCTRL_RATE_ICODE_FAST   = 0x30,
+
+       /* bit 7 SendOnePuls */
+       RC632_CDRCTRL_15693_EOF_PULSE   = 0x80,
 };
 
 enum rc632_erg_type_b_framing {
@@ -155,6 +190,7 @@ enum rc632_reg_rx_control1 {
        RC632_RXCTRL1_ISO15693          = 0x08,
        RC632_RXCTRL1_ISO14443          = 0x10,
 
+#define RC632_RXCTRL1_SUBCP_MASK       0xe0
        RC632_RXCTRL1_SUBCP_1           = 0x00,
        RC632_RXCTRL1_SUBCP_2           = 0x20,
        RC632_RXCTRL1_SUBCP_4           = 0x40,
@@ -211,4 +247,26 @@ enum rc632_reg_channel_redundancy {
        RC632_CR_CRC3309                = 0x20,
 };
 
+enum rc632_reg_timer_control {
+       RC632_TMR_START_TX_BEGIN        = 0x01,
+       RC632_TMR_START_TX_END          = 0x02,
+       RC632_TMR_STOP_RX_BEGIN         = 0x04,
+       RC632_TMR_STOP_RX_END           = 0x08,
+};
+ 
+enum rc632_reg_timer_irq {
+       RC632_IRQ_LO_ALERT              = 0x01,
+       RC632_IRQ_HI_ALERT              = 0x02,
+       RC632_IRQ_IDLE                  = 0x04,
+       RC632_IRQ_RX                    = 0x08,
+       RC632_IRQ_TX                    = 0x10,
+       RC632_IRQ_TIMER                 = 0x20,
+
+       RC632_IRQ_SET                   = 0x80,
+};
 
+enum rc632_reg_secondary_status {
+       RC632_SEC_ST_TMR_RUNNING        = 0x80,
+       RC632_SEC_ST_E2_READY           = 0x40,
+       RC632_SEC_ST_CRC_READY          = 0x20,
+};