const struct iso15693_anticol_cmd *acf,
unsigned int acf_len,
struct iso15693_anticol_resp *resp,
- unsigned int *rx_len, char *bit_of_col);
+ unsigned int *rx_len, unsigned char *bit_of_col);
} iso15693;
struct {
int (*setkey)(struct rfid_asic_handle *h,
DEBUGPC(", mTXsof"); \
DEBUGPC("\n"); } while (0);
-#define DEBUGP_INTERRUPT_FLAG(foo) do {\
- DEBUGP("interrupt_flag: 0x%0.2x",foo); \
+#define DEBUGP_INTERRUPT_FLAG(txt,foo) do {\
+ DEBUGP("%s: 0x%0.2x",txt,foo); \
if (foo & RC632_INT_HIALERT) \
DEBUGPC(", HiA"); \
if (foo & RC632_INT_LOALERT) \
u_int64_t timeout)
{
int ret;
- u_int8_t prescaler, divisor;
+ u_int8_t prescaler, divisor, irq;
timeout *= TIMER_RELAX_FACTOR;
RC632_TMR_START_TX_END|RC632_TMR_STOP_RX_BEGIN);
/* clear timer irq bit */
- ret = rc632_set_bits(handle, RC632_REG_INTERRUPT_RQ, RC632_IRQ_TIMER);
+ ret = rc632_clear_irqs(handle, RC632_IRQ_TIMER);
+
+ /* enable timer IRQ */
+ ret |= rc632_reg_write(handle, RC632_REG_INTERRUPT_EN, RC632_IRQ_SET | RC632_IRQ_TIMER);
ret |= rc632_reg_write(handle, RC632_REG_TIMER_RELOAD, divisor);
int ret;
u_int8_t stat, irq, cmd;
+ ret = rc632_reg_read(handle, RC632_REG_INTERRUPT_EN, &irq);
+ if (ret < 0)
+ return ret;
+ DEBUGP_INTERRUPT_FLAG("irq_en",irq);
+
+ ret = rc632_reg_write(handle, RC632_REG_INTERRUPT_EN, RC632_IRQ_SET
+ | RC632_IRQ_TIMER
+ | RC632_IRQ_IDLE
+ | RC632_IRQ_RX );
+ if (ret < 0)
+ return ret;
+
while (1) {
rc632_reg_read(handle, RC632_REG_PRIMARY_STATUS, &stat);
DEBUGP_STATUS_FLAG(stat);
if (err & (RC632_ERR_FLAG_COL_ERR |
RC632_ERR_FLAG_PARITY_ERR |
RC632_ERR_FLAG_FRAMING_ERR |
- RC632_ERR_FLAG_CRC_ERR))
+ /* FIXME: why get we CRC errors in CL2 anticol at iso14443a operation with mifare UL? */
+ /* RC632_ERR_FLAG_CRC_ERR | */
+ 0))
return -EIO;
}
if (stat & RC632_STAT_IRQ) {
ret = rc632_reg_read(handle, RC632_REG_INTERRUPT_RQ, &irq);
if (ret < 0)
return ret;
- DEBUGP_INTERRUPT_FLAG(irq);
+ DEBUGP_INTERRUPT_FLAG("irq_rq",irq);
if (irq & RC632_IRQ_TIMER && !(irq & RC632_IRQ_RX)) {
DEBUGP("timer expired before RX!!\n");
+ rc632_clear_irqs(handle, RC632_IRQ_TIMER);
return -ETIMEDOUT;
}
}
if (ret < 0)
return ret;
- if (cmd == 0)
+ if (cmd == 0) {
+ rc632_clear_irqs(handle, RC632_IRQ_RX);
return 0;
+ }
/* poll every millisecond */
usleep(1000);
/* check if IRQ has occurred (IRQ flag set)*/
if (foo & RC632_STAT_IRQ) {
ret = rc632_reg_read(handle, RC632_REG_INTERRUPT_RQ, &foo);
- DEBUGP_INTERRUPT_FLAG(foo);
+ DEBUGP_INTERRUPT_FLAG("irq_rq",foo);
/* clear all interrupts */
rc632_clear_irqs(handle, 0xff);
}
}, {
.reg = RC632_REG_CRC_PRESET_MSB,
.val = 0xff,
+ /* }, {
+ .reg = RC632_REG_INTERRUPT_EN,
+ .val = RC632_INT_IDLE |
+ RC632_INT_TIMER |
+ RC632_INT_RX |
+ RC632_INT_TX, */
}
};
const struct iso15693_anticol_cmd *acf,
unsigned int acf_len,
struct iso15693_anticol_resp *resp,
- unsigned int *rx_len, char *bit_of_col)
+ unsigned int *rx_len, unsigned char *bit_of_col)
{
u_int8_t error_flag, boc;
//u_int8_t rx_len;
return ret;
DEBUGP_ERROR_FLAG(error_flag);
+ //FIXME: check for framing and crc errors...
if (error_flag & RC632_ERR_FLAG_COL_ERR) {
/* retrieve bit of collission */
ret = rc632_reg_read(handle, RC632_REG_COLL_POS, &boc);
if (ret < 0)
return ret;
*bit_of_col = boc;
+ } else {
+ *bit_of_col = 0;
}
return 0;
iso14443a_code_nvb_bits(&acf.nvb, 16);
ret = iso14443a_transceive_acf(handle, &acf, &bit_of_col);
+ DEBUGP("tran_acf->%d boc: %d\n",ret,bit_of_col);
if (ret < 0)
return ret;
switch (acf.sel_code) {
case ISO14443A_AC_SEL_CODE_CL1:
/* cascading from CL1 to CL2 */
+ DEBUGP("cascading from CL1 to CL2\n");
if (acf.uid_bits[0] != 0x88) {
DEBUGP("Cascade bit set, but UID0 != 0x88\n");
return -1;
break;
case ISO14443A_AC_SEL_CODE_CL2:
/* cascading from CL2 to CL3 */
+ DEBUGP("cascading from CL2 to CL3\n");
memcpy(&handle->uid[3], &acf.uid_bits[1], 3);
acf.sel_code = ISO14443A_AC_SEL_CODE_CL3;
h->level = ISO14443A_LEVEL_CL3;