2 * linux/arch/alpha/kernel/sys_eiger.c
4 * Copyright (C) 1995 David A Rusling
5 * Copyright (C) 1996, 1999 Jay A Estabrook
6 * Copyright (C) 1998, 1999 Richard Henderson
7 * Copyright (C) 1999 Iain Grant
9 * Code supporting the EIGER (EV6+TSUNAMI).
12 #include <linux/kernel.h>
13 #include <linux/types.h>
15 #include <linux/sched.h>
16 #include <linux/pci.h>
17 #include <linux/init.h>
19 #include <asm/ptrace.h>
20 #include <asm/system.h>
23 #include <asm/bitops.h>
24 #include <asm/mmu_context.h>
27 #include <asm/pgtable.h>
28 #include <asm/core_tsunami.h>
29 #include <asm/hwrpb.h>
34 #include "machvec_impl.h"
37 /* Note that this interrupt code is identical to TAKARA. */
39 /* Note mask bit is true for DISABLED irqs. */
40 static unsigned long cached_irq_mask[2] = { -1, -1 };
43 eiger_update_irq_hw(unsigned long irq, unsigned long mask)
47 mask = (irq >= 64 ? mask << 16 : mask >> ((irq - 16) & 0x30));
48 regaddr = 0x510 + (((irq - 16) >> 2) & 0x0c);
49 outl(mask & 0xffff0000UL, regaddr);
53 eiger_enable_irq(unsigned int irq)
56 mask = (cached_irq_mask[irq >= 64] &= ~(1UL << (irq & 63)));
57 eiger_update_irq_hw(irq, mask);
61 eiger_disable_irq(unsigned int irq)
64 mask = (cached_irq_mask[irq >= 64] |= 1UL << (irq & 63));
65 eiger_update_irq_hw(irq, mask);
69 eiger_startup_irq(unsigned int irq)
71 eiger_enable_irq(irq);
72 return 0; /* never anything pending */
76 eiger_end_irq(unsigned int irq)
78 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
79 eiger_enable_irq(irq);
82 static struct hw_interrupt_type eiger_irq_type = {
84 startup: eiger_startup_irq,
85 shutdown: eiger_disable_irq,
86 enable: eiger_enable_irq,
87 disable: eiger_disable_irq,
88 ack: eiger_disable_irq,
93 eiger_device_interrupt(unsigned long vector, struct pt_regs * regs)
98 * The PALcode will have passed us vectors 0x800 or 0x810,
99 * which are fairly arbitrary values and serve only to tell
100 * us whether an interrupt has come in on IRQ0 or IRQ1. If
101 * it's IRQ1 it's a PCI interrupt; if it's IRQ0, it's
102 * probably ISA, but PCI interrupts can come through IRQ0
103 * as well if the interrupt controller isn't in accelerated
106 * OTOH, the accelerator thing doesn't seem to be working
107 * overly well, so what we'll do instead is try directly
108 * examining the Master Interrupt Register to see if it's a
109 * PCI interrupt, and if _not_ then we'll pass it on to the
113 intstatus = inw(0x500) & 15;
116 * This is a PCI interrupt. Check each bit and
117 * despatch an interrupt if it's set.
120 if (intstatus & 8) handle_irq(16+3, regs);
121 if (intstatus & 4) handle_irq(16+2, regs);
122 if (intstatus & 2) handle_irq(16+1, regs);
123 if (intstatus & 1) handle_irq(16+0, regs);
125 isa_device_interrupt(vector, regs);
130 eiger_srm_device_interrupt(unsigned long vector, struct pt_regs * regs)
132 int irq = (vector - 0x800) >> 4;
133 handle_irq(irq, regs);
141 outb(0, DMA1_RESET_REG);
142 outb(0, DMA2_RESET_REG);
143 outb(DMA_MODE_CASCADE, DMA2_MODE_REG);
144 outb(0, DMA2_MASK_REG);
147 alpha_mv.device_interrupt = eiger_srm_device_interrupt;
149 for (i = 16; i < 128; i += 16)
150 eiger_update_irq_hw(i, -1);
154 for (i = 16; i < 128; ++i) {
155 irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL;
156 irq_desc[i].handler = &eiger_irq_type;
161 eiger_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
165 /* The SRM console has already calculated out the IRQ value's for
166 option cards. As this works lets just read in the value already
167 set and change it to a useable value by Linux.
169 All the IRQ values generated by the console are greater than 90,
170 so we subtract 80 because it is (90 - allocated ISA IRQ's). */
172 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq_orig);
174 return irq_orig - 0x80;
178 eiger_swizzle(struct pci_dev *dev, u8 *pinp)
180 struct pci_controller *hose = dev->sysdata;
181 int slot, pin = *pinp;
182 int bridge_count = 0;
184 /* Find the number of backplane bridges. */
185 int backplane = inw(0x502) & 0x0f;
189 case 0x00: bridge_count = 0; break; /* No bridges */
190 case 0x01: bridge_count = 1; break; /* 1 */
191 case 0x03: bridge_count = 2; break; /* 2 */
192 case 0x07: bridge_count = 3; break; /* 3 */
193 case 0x0f: bridge_count = 4; break; /* 4 */
196 slot = PCI_SLOT(dev->devfn);
197 while (dev->bus->self) {
198 /* Check for built-in bridges on hose 0. */
200 && (PCI_SLOT(dev->bus->self->devfn)
201 > 20 - bridge_count)) {
202 slot = PCI_SLOT(dev->devfn);
205 /* Must be a card-based bridge. */
206 pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn));
208 /* Move up the chain of bridges. */
209 dev = dev->bus->self;
219 struct alpha_machine_vector eiger_mv __initmv = {
220 vector_name: "Eiger",
225 machine_check: tsunami_machine_check,
226 max_dma_address: ALPHA_MAX_DMA_ADDRESS,
227 min_io_address: DEFAULT_IO_BASE,
228 min_mem_address: DEFAULT_MEM_BASE,
229 pci_dac_offset: TSUNAMI_DAC_OFFSET,
232 device_interrupt: eiger_device_interrupt,
234 init_arch: tsunami_init_arch,
235 init_irq: eiger_init_irq,
236 init_rtc: common_init_rtc,
237 init_pci: common_init_pci,
238 kill_arch: tsunami_kill_arch,
239 pci_map_irq: eiger_map_irq,
240 pci_swizzle: eiger_swizzle,