arch/arm/lib/io-writesw-armv4.S

   1 /*
   2  *  linux/arch/arm/lib/io-writesw-armv4.S
   3  *
   4  *  Copyright (C) 1995-2000 Russell King
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10 #include <linux/linkage.h>
  11 #include <asm/assembler.h>
  12 #include <asm/hardware.h>
  13
  14 .outsw_bad_alignment:
  15                 adr     r0, .outsw_bad_align_msg
  16                 mov     r2, lr
  17                 b       SYMBOL_NAME(panic)
  18 .outsw_bad_align_msg:
  19                 .asciz  "outsw: bad buffer alignment (0x%p, lr=0x%08lX)\n"
  20                 .align
  21
  22 .outsw_align:   tst     r1, #1
  23                 bne     .outsw_bad_alignment
  24
  25                 ldrh    r3, [r1], #2
  26                 strh    r3, [r0]
  27
  28                 subs    r2, r2, #1
  29                 RETINSTR(moveq, pc, lr)
  30
  31 ENTRY(__raw_writesw)
  32                 teq     r2, #0          @ do we have to check for the zero len?
  33                 moveq   pc, lr
  34                 tst     r1, #3
  35                 bne     .outsw_align
  36
  37                 stmfd   sp!, {r4, r5, lr}
  38
  39                 subs    r2, r2, #8
  40                 bmi     .no_outsw_8
  41
  42 .outsw_8_lp:    ldmia   r1!, {r3, r4, r5, ip}
  43
  44                 strh    r3, [r0]
  45                 mov     r3, r3, lsr #16
  46                 strh    r3, [r0]
  47                 strh    r4, [r0]
  48                 mov     r4, r4, lsr #16
  49                 strh    r4, [r0]
  50                 strh    r5, [r0]
  51                 mov     r5, r5, lsr #16
  52                 strh    r5, [r0]
  53                 strh    ip, [r0]
  54                 mov     ip, ip, lsr #16
  55                 strh    ip, [r0]
  56
  57                 subs    r2, r2, #8
  58                 bpl     .outsw_8_lp
  59
  60                 tst     r2, #7
  61                 LOADREGS(eqfd, sp!, {r4, r5, pc})
  62
  63 .no_outsw_8:    tst     r2, #4
  64                 beq     .no_outsw_4
  65
  66                 ldmia   r1!, {r3, ip}
  67                 strh    r3, [r0]
  68                 mov     r3, r3, lsr #16
  69                 strh    r3, [r0]
  70                 strh    ip, [r0]
  71                 mov     ip, ip, lsr #16
  72                 strh    ip, [r0]
  73
  74 .no_outsw_4:    tst     r2, #2
  75                 beq     .no_outsw_2
  76
  77                 ldr     r3, [r1], #4
  78                 strh    r3, [r0]
  79                 mov     r3, r3, lsr #16
  80                 strh    r3, [r0]
  81
  82 .no_outsw_2:    tst     r2, #1
  83                 ldrneh  r3, [r1]
  84                 strneh  r3, [r0]
  85
  86                 LOADREGS(fd, sp!, {r4, r5, pc})