2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2000-2003 Silicon Graphics, Inc. All rights reserved.
10 #include <linux/module.h>
12 #include <asm/delay.h>
13 #include <asm/sn/simulator.h>
14 #include <asm/sn/pda.h>
15 #include <asm/sn/sn_cpuid.h>
18 * sn_io_addr - convert an in/out port to an i/o address
19 * @port: port to convert
21 * Legacy in/out instructions are converted to ld/st instructions
22 * on IA64. This routine will convert a port number into a valid
23 * SN i/o address. Used by sn_in*() and sn_out*().
26 sn_io_addr(unsigned long port)
28 if (!IS_RUNNING_ON_SIMULATOR()) {
29 /* On sn2, legacy I/O ports don't point at anything */
32 return( (void *) (port | __IA64_UNCACHED_OFFSET));
34 /* but the simulator uses them... */
38 * word align port, but need more than 10 bits
39 * for accessing registers in bedrock local block
40 * (so we don't do port&0xfff)
42 addr = 0xc0000087cc000000 | ((port >> 2) << 12);
43 if ((port >= 0x1f0 && port <= 0x1f7) || port == 0x3f6 || port == 0x3f7)
49 EXPORT_SYMBOL(sn_io_addr);
52 * sn_mmiob - I/O space memory barrier
54 * Acts as a memory mapped I/O barrier for platforms that queue writes to
55 * I/O space. This ensures that subsequent writes to I/O space arrive after
56 * all previous writes. For most ia64 platforms, this is a simple
57 * 'mf.a' instruction. For other platforms, mmiob() may have to read
58 * a chipset register to ensure ordering.
60 * On SN2, we wait for the PIO_WRITE_STATUS SHub register to clear.
61 * See PV 871084 for details about the WAR about zero value.
67 while ((((volatile unsigned long) (*pda.pio_write_status_addr)) & SH_PIO_WRITE_STATUS_0_PENDING_WRITE_COUNT_MASK) !=
68 SH_PIO_WRITE_STATUS_0_PENDING_WRITE_COUNT_MASK)