2 * arch/mips/ddb5476/nile4.c --
3 * low-level PIC code for NEC Vrc-5476 (Nile 4)
5 * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
6 * Sony Software Development Center Europe (SDCE), Brussels
8 * Copyright 2001 MontaVista Software Inc.
9 * Author: jsun@mvista.com or jsun@junsun.net
12 #include <linux/kernel.h>
13 #include <linux/types.h>
14 #include <linux/interrupt.h>
15 #include <linux/ioport.h>
17 #include <asm/addrspace.h>
19 #include <asm/ddb5xxx/ddb5xxx.h>
24 * Interrupt Programming
26 void nile4_map_irq(int nile4_irq, int cpu_irq)
36 t &= ~(7 << (nile4_irq * 4));
37 t |= cpu_irq << (nile4_irq * 4);
41 void nile4_map_irq_all(int cpu_irq)
49 t = ddb_in32(DDB_INTCTRL);
52 ddb_out32(DDB_INTCTRL, t);
53 t = ddb_in32(DDB_INTCTRL + 4);
56 ddb_out32(DDB_INTCTRL + 4, t);
59 void nile4_enable_irq(unsigned int nile4_irq)
75 t |= 8 << (nile4_irq * 4);
80 void nile4_disable_irq(unsigned int nile4_irq)
92 t &= ~(8 << (nile4_irq * 4));
96 void nile4_disable_irq_all(void)
98 ddb_out32(DDB_INTCTRL, 0);
99 ddb_out32(DDB_INTCTRL + 4, 0);
102 u16 nile4_get_irq_stat(int cpu_irq)
104 return ddb_in16(DDB_INTSTAT0 + cpu_irq * 2);
107 void nile4_enable_irq_output(int cpu_irq)
111 t = ddb_in32(DDB_INTSTAT1 + 4);
112 t |= 1 << (16 + cpu_irq);
113 ddb_out32(DDB_INTSTAT1, t);
116 void nile4_disable_irq_output(int cpu_irq)
120 t = ddb_in32(DDB_INTSTAT1 + 4);
121 t &= ~(1 << (16 + cpu_irq));
122 ddb_out32(DDB_INTSTAT1, t);
125 void nile4_set_pci_irq_polarity(int pci_irq, int high)
129 t = ddb_in32(DDB_INTPPES);
131 t &= ~(1 << (pci_irq * 2));
133 t |= 1 << (pci_irq * 2);
134 ddb_out32(DDB_INTPPES, t);
137 void nile4_set_pci_irq_level_or_edge(int pci_irq, int level)
141 t = ddb_in32(DDB_INTPPES);
143 t |= 2 << (pci_irq * 2);
145 t &= ~(2 << (pci_irq * 2));
146 ddb_out32(DDB_INTPPES, t);
149 void nile4_clear_irq(int nile4_irq)
152 ddb_out32(DDB_INTCLR, 1 << nile4_irq);
155 void nile4_clear_irq_mask(u32 mask)
157 ddb_out32(DDB_INTCLR, mask);
160 u8 nile4_i8259_iack(void)
165 /* Set window 0 for interrupt acknowledge */
166 reg = ddb_in32(DDB_PCIINIT0);
168 ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IACK, 0, DDB_PCI_ACCESS_32);
169 irq = *(volatile u8 *) KSEG1ADDR(DDB_PCI_IACK_BASE);
170 /* restore window 0 for PCI I/O space */
171 // ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IO, 0, DDB_PCI_ACCESS_32);
172 ddb_out32(DDB_PCIINIT0, reg);
174 /* i8269.c set the base vector to be 0x0 */
178 static unsigned int nile4_irq_startup(unsigned int irq) {
180 nile4_enable_irq(irq);
185 static void nile4_ack_irq(unsigned int irq) {
189 nile4_clear_irq(irq);
191 nile4_disable_irq(irq);
196 static void nile4_irq_end(unsigned int irq) {
199 if(!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
201 nile4_enable_irq(irq);
208 #define nile4_irq_shutdown nile4_disable_irq
210 static hw_irq_controller nile4_irq_controller = {
221 void nile4_irq_setup(u32 base) {
224 extern irq_desc_t irq_desc[];
228 /* Map all interrupts to CPU int #0 */
229 nile4_map_irq_all(0);
231 /* PCI INTA#-E# must be level triggered */
232 nile4_set_pci_irq_level_or_edge(0, 1);
233 nile4_set_pci_irq_level_or_edge(1, 1);
234 nile4_set_pci_irq_level_or_edge(2, 1);
235 nile4_set_pci_irq_level_or_edge(3, 1);
236 nile4_set_pci_irq_level_or_edge(4, 1);
238 /* PCI INTA#-D# must be active low, INTE# must be active high */
239 nile4_set_pci_irq_polarity(0, 0);
240 nile4_set_pci_irq_polarity(1, 0);
241 nile4_set_pci_irq_polarity(2, 0);
242 nile4_set_pci_irq_polarity(3, 0);
243 nile4_set_pci_irq_polarity(4, 1);
246 for (i = 0; i < 16; i++) {
248 nile4_disable_irq(i);
251 /* Enable CPU int #0 */
252 nile4_enable_irq_output(0);
254 for (i= base; i< base + NUM_NILE4_INTERRUPTS; i++) {
255 irq_desc[i].status = IRQ_DISABLED;
256 irq_desc[i].action = NULL;
257 irq_desc[i].depth = 1;
258 irq_desc[i].handler = &nile4_irq_controller;
263 #if defined(CONFIG_RUNTIME_DEBUG)
264 void nile4_dump_irq_status(void)
267 CPUSTAT = %p:%p\n", (void *) ddb_in32(DDB_CPUSTAT + 4),
268 (void *) ddb_in32(DDB_CPUSTAT));
270 INTCTRL = %p:%p\n", (void *) ddb_in32(DDB_INTCTRL + 4),
271 (void *) ddb_in32(DDB_INTCTRL));
273 "INTSTAT0 = %p:%p\n",
274 (void *) ddb_in32(DDB_INTSTAT0 + 4),
275 (void *) ddb_in32(DDB_INTSTAT0));
277 "INTSTAT1 = %p:%p\n",
278 (void *) ddb_in32(DDB_INTSTAT1 + 4),
279 (void *) ddb_in32(DDB_INTSTAT1));
281 "INTCLR = %p:%p\n", (void *) ddb_in32(DDB_INTCLR + 4),
282 (void *) ddb_in32(DDB_INTCLR));
284 "INTPPES = %p:%p\n", (void *) ddb_in32(DDB_INTPPES + 4),
285 (void *) ddb_in32(DDB_INTPPES));