3 * BRIEF MODULE DESCRIPTION
4 * Galileo EV96100 rtc routines.
6 * Copyright 2000 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc.
8 * ppopov@mvista.com or source@mvista.com
10 * This file was derived from Carsten Langgaard's
11 * arch/mips/mips-boards/atlas/atlas_rtc.c.
13 * Carsten Langgaard, carstenl@mips.com
14 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the
18 * Free Software Foundation; either version 2 of the License, or (at your
19 * option) any later version.
21 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
22 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
24 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
27 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
28 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 * You should have received a copy of the GNU General Public License along
33 * with this program; if not, write to the Free Software Foundation, Inc.,
34 * 675 Mass Ave, Cambridge, MA 02139, USA.
36 #include <linux/init.h>
37 #include <linux/kernel_stat.h>
38 #include <linux/sched.h>
39 #include <linux/spinlock.h>
40 #include <linux/timex.h>
42 #include <asm/compiler.h>
43 #include <asm/mipsregs.h>
44 #include <asm/ptrace.h>
47 #define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
49 extern volatile unsigned long wall_jiffies;
50 unsigned long missed_heart_beats = 0;
52 static unsigned long r4k_offset; /* Amount to increment compare reg each time */
53 static unsigned long r4k_cur; /* What counter should be at next timer irq */
54 extern rwlock_t xtime_lock;
56 static inline void ack_r4ktimer(unsigned long newval)
58 write_c0_compare(newval);
61 static int set_rtc_mmss(unsigned long nowtime)
63 /* EV96100 does not have a real time clock */
72 * Figure out the r4k offset, the amount to increment the compare
73 * register for each time tick.
74 * Use the RTC to calculate offset.
76 static unsigned long __init cal_r4koff(void)
84 static unsigned long __init get_mips_time(void)
86 unsigned int year, mon, day, hour, min, sec;
94 return mktime(year, mon, day, hour, min, sec);
99 * called from start_kernel()
101 void __init time_init(void)
104 unsigned int est_freq;
106 r4k_offset = cal_r4koff();
108 est_freq = 2*r4k_offset*HZ;
109 est_freq += 5000; /* round */
110 est_freq -= est_freq%10000;
111 printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
112 (est_freq%1000000)*100/1000000);
113 r4k_cur = (read_c0_count() + r4k_offset);
115 write_c0_compare(r4k_cur);
117 change_c0_status(ST0_IM, IE_IRQ5); /* FIX ME */
120 /* This is for machines which generate the exact clock. */
121 #define USECS_PER_JIFFY (1000000/HZ)
123 /* Cycle counter value at the previous timer interrupt.. */
125 static unsigned int timerhi = 0, timerlo = 0;
128 * FIXME: Does playing with the RP bit in c0_status interfere with this code?
130 static unsigned long do_fast_gettimeoffset(void)
133 unsigned long res, tmp;
135 /* Last jiffy when do_fast_gettimeoffset() was called. */
136 static unsigned long last_jiffies=0;
137 unsigned long quotient;
140 * Cached "1/(clocks per usec)*2^32" value.
141 * It has to be recalculated once each jiffy.
143 static unsigned long cached_quotient=0;
147 quotient = cached_quotient;
149 if (tmp && last_jiffies != tmp) {
151 __asm__(".set\tnoreorder\n\t"
155 "dsll32\t$1,%1,0\n\t"
157 "ddivu\t$0,$1,%3\n\t"
159 "dsll32\t%0,%4,0\n\t"
161 "ddivu\t$0,%0,$1\n\t"
167 : "r" (timerhi), "m" (timerlo),
168 "r" (tmp), "r" (USECS_PER_JIFFY)
169 : "hi", "lo", GCC_REG_ACCUM);
170 cached_quotient = quotient;
173 /* Get last timer tick in absolute kernel time */
174 count = read_c0_count();
176 /* .. relative to previous jiffy (32 bits is enough) */
179 __asm__("multu\t%1,%2\n\t"
182 : "r" (count), "r" (quotient)
183 : "hi", "lo", GCC_REG_ACCUM);
186 * Due to possible jiffies inconsistencies, we need to check
187 * the result so that we'll get a timer that is monotonic.
189 if (res >= USECS_PER_JIFFY)
190 res = USECS_PER_JIFFY-1;
195 void do_gettimeofday(struct timeval *tv)
199 read_lock_irqsave (&xtime_lock, flags);
201 tv->tv_usec += do_fast_gettimeoffset();
204 * xtime is atomically updated in timer_bh. jiffies - wall_jiffies
205 * is nonzero if the timer bottom half hasnt executed yet.
207 if (jiffies - wall_jiffies)
208 tv->tv_usec += USECS_PER_JIFFY;
210 read_unlock_irqrestore (&xtime_lock, flags);
212 if (tv->tv_usec >= 1000000) {
213 tv->tv_usec -= 1000000;
218 void do_settimeofday(struct timeval *tv)
220 write_lock_irq (&xtime_lock);
222 /* This is revolting. We need to set the xtime.tv_usec correctly.
223 * However, the value in this location is value at the last tick.
224 * Discover what correction gettimeofday would have done, and then
227 tv->tv_usec -= do_fast_gettimeoffset();
229 if (tv->tv_usec < 0) {
230 tv->tv_usec += 1000000;
235 time_adjust = 0; /* stop active adjtime() */
236 time_status |= STA_UNSYNC;
237 time_maxerror = NTP_PHASE_LIMIT;
238 time_esterror = NTP_PHASE_LIMIT;
240 write_unlock_irq (&xtime_lock);
244 * There are a lot of conceptually broken versions of the MIPS timer interrupt
245 * handler floating around. This one is rather different, but the algorithm
246 * is probably more robust.
248 void mips_timer_interrupt(struct pt_regs *regs)
250 int irq = 7; /* FIX ME */
252 if (r4k_offset == 0) {
257 kstat.irqs[0][irq]++;
259 r4k_cur += r4k_offset;
260 ack_r4ktimer(r4k_cur);
262 } while (((unsigned long)read_c0_count()
263 - r4k_cur) < 0x7fffffff);