2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994, 1995 Waldorf Electronics
7 * Written by Ralf Baechle and Andreas Busse
8 * Copyright (C) 1995 - 1999 Ralf Baechle
9 * Copyright (C) 1996 Paul M. Antoine
10 * Modified for DECStation and hence R3000 support by Paul M. Antoine
11 * Further modifications by David S. Miller and Harald Koerfgen
12 * Copyright (C) 1999 Silicon Graphics, Inc.
14 * Kevin Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
15 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
17 #include <linux/config.h>
18 #include <linux/init.h>
19 #include <linux/threads.h>
22 #include <asm/current.h>
23 #include <asm/offset.h>
24 #include <asm/pgtable-bits.h>
25 #include <asm/processor.h>
26 #include <asm/regdef.h>
27 #include <asm/cachectl.h>
28 #include <asm/mipsregs.h>
29 #include <asm/stackframe.h>
33 * Reserved space for exception handlers.
34 * Necessary for machines which link their kernels at KSEG0.
38 /* The following two symbols are used for kernel profiling. */
45 LEAF(except_vec2_generic)
50 * This is a very bad place to be. Our cache error
51 * detection has triggered. If we have write-back data
52 * in the cache, we may not be able to recover. As a
53 * first-order desperate measure, turn off KSEG0 cacheing.
58 ori k0,k0,CONF_CM_UNCACHED
60 /* Give it a few cycles to sink in... */
67 END(except_vec2_generic)
72 * Special interrupt vector for embedded MIPS. This is a
73 * dedicated interrupt vector which reduces interrupt processing
74 * overhead. The jump instruction will be inserted here at
75 * initialization time. This handler may only be 8 bytes in
78 NESTED(except_vec4, 0, sp)
79 1: j 1b /* Dummy, will be replaced */
84 * EJTAG debug exception handler.
85 * The EJTAG debug exception entry point is 0xbfc00480, which
86 * normally is in the boot PROM, so the boot PROM must do a
87 * unconditional jump to this vector.
89 NESTED(except_vec_ejtag_debug, 0, sp)
92 END(except_vec_ejtag_debug)
97 * EJTAG debug exception handler.
99 NESTED(ejtag_debug_handler, PT_SIZE, sp)
105 sll k0, k0, 30 # Check for SDBBP.
106 bgez k0, ejtag_return
108 la k0, ejtag_debug_buffer
111 jal ejtag_exception_handler
114 la k0, ejtag_debug_buffer
124 END(ejtag_debug_handler)
129 * NMI debug exception handler for MIPS reference boards.
130 * The NMI debug exception entry point is 0xbfc00000, which
131 * normally is in the boot PROM, so the boot PROM must do a
132 * unconditional jump to this vector.
134 NESTED(except_vec_nmi, 0, sp)
141 NESTED(nmi_handler, PT_SIZE, sp)
146 jal nmi_exception_handler
159 NESTED(kernel_entry, 16, sp)
163 * The firmware/bootloader passes argc/argp/envp
164 * to us as arguments. But clear bss first because
165 * the romvec and other important info is stored there
177 * Stack for kernel and init, current variable
179 la $28, init_task_union
180 addiu t0, $28, KERNEL_STACK_SIZE-32
192 * SMP slave cpus entry point. Board specific code for bootstrap calls this
193 * function after setting up the stack and gp registers.
201 li t1, ~(ST0_CU1|ST0_CU2|ST0_CU3|ST0_KX|ST0_SX|ST0_UX)
213 * This buffer is reserved for the use of the EJTAG debug
217 EXPORT(ejtag_debug_buffer)
220 .comm kernelsp, NR_CPUS * 8, 8
221 .comm pgd_current, NR_CPUS * 8, 8
223 .macro page name, order=0
225 \name: .size \name, (_PAGE_SIZE << \order)
226 .org . + (_PAGE_SIZE << \order)
233 page swapper_pg_dir, _PGD_ORDER
234 page empty_bad_page, 0
235 page empty_bad_page_table, 0
236 page invalid_pte_table, 0